diff options
| author | Steve French <sfrench@us.ibm.com> | 2006-03-03 11:27:25 +0000 |
|---|---|---|
| committer | Steve French <sfrench@us.ibm.com> | 2006-03-03 11:27:25 +0000 |
| commit | c6ee60b7c8bbc78e3b1776b2820a7e7f95f8996a (patch) | |
| tree | 99b48ef0f5217fddc0aa897d9e60d95ace7da6ff /arch/mips/mm | |
| parent | 13298defe5323c7fdcac268f588d8d1090758fb8 (diff) | |
| parent | c499ec24c31edf270e777a868ffd0daddcfe7ebd (diff) | |
| download | kernel-crypto-c6ee60b7c8bbc78e3b1776b2820a7e7f95f8996a.tar.gz kernel-crypto-c6ee60b7c8bbc78e3b1776b2820a7e7f95f8996a.tar.xz kernel-crypto-c6ee60b7c8bbc78e3b1776b2820a7e7f95f8996a.zip | |
Merge with /pub/scm/linux/kernel/git/torvalds/linux-2.6.git
Signed-off-by: Steve French <sfrench@us.ibm.com>
Diffstat (limited to 'arch/mips/mm')
| -rw-r--r-- | arch/mips/mm/c-r4k.c | 16 |
1 files changed, 11 insertions, 5 deletions
diff --git a/arch/mips/mm/c-r4k.c b/arch/mips/mm/c-r4k.c index 1b71d91e826..0668e9bfce4 100644 --- a/arch/mips/mm/c-r4k.c +++ b/arch/mips/mm/c-r4k.c @@ -235,7 +235,9 @@ static inline void r4k_blast_scache_page_setup(void) { unsigned long sc_lsize = cpu_scache_line_size(); - if (sc_lsize == 16) + if (scache_size == 0) + r4k_blast_scache_page = (void *)no_sc_noop; + else if (sc_lsize == 16) r4k_blast_scache_page = blast_scache16_page; else if (sc_lsize == 32) r4k_blast_scache_page = blast_scache32_page; @@ -251,7 +253,9 @@ static inline void r4k_blast_scache_page_indexed_setup(void) { unsigned long sc_lsize = cpu_scache_line_size(); - if (sc_lsize == 16) + if (scache_size == 0) + r4k_blast_scache_page_indexed = (void *)no_sc_noop; + else if (sc_lsize == 16) r4k_blast_scache_page_indexed = blast_scache16_page_indexed; else if (sc_lsize == 32) r4k_blast_scache_page_indexed = blast_scache32_page_indexed; @@ -267,7 +271,9 @@ static inline void r4k_blast_scache_setup(void) { unsigned long sc_lsize = cpu_scache_line_size(); - if (sc_lsize == 16) + if (scache_size == 0) + r4k_blast_scache = (void *)no_sc_noop; + else if (sc_lsize == 16) r4k_blast_scache = blast_scache16; else if (sc_lsize == 32) r4k_blast_scache = blast_scache32; @@ -482,7 +488,7 @@ static inline void local_r4k_flush_icache_range(void *args) protected_blast_dcache_range(start, end); } - if (!cpu_icache_snoops_remote_store) { + if (!cpu_icache_snoops_remote_store && scache_size) { if (end - start > scache_size) r4k_blast_scache(); else @@ -651,7 +657,7 @@ static void local_r4k_flush_cache_sigtramp(void * arg) R4600_HIT_CACHEOP_WAR_IMPL; protected_writeback_dcache_line(addr & ~(dc_lsize - 1)); - if (!cpu_icache_snoops_remote_store) + if (!cpu_icache_snoops_remote_store && scache_size) protected_writeback_scache_line(addr & ~(sc_lsize - 1)); protected_flush_icache_line(addr & ~(ic_lsize - 1)); if (MIPS4K_ICACHE_REFILL_WAR) { |