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authorMatt LaPlante <kernel1@cyberdogtech.com>2009-01-26 11:12:25 +0100
committerJiri Kosina <jkosina@suse.cz>2009-03-30 15:22:01 +0200
commit692105b8ac5bcd75dc65f6a8f10bdbd0f0f34dcf (patch)
treee079cea0948d250e5411befe0c5cca7c97bcf860 /arch/avr32
parent877d03105d04b2c13e241130277fa69c8d2564f0 (diff)
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trivial: fix typos/grammar errors in Kconfig texts
Signed-off-by: Matt LaPlante <kernel1@cyberdogtech.com> Acked-by: Randy Dunlap <randy.dunlap@oracle.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Diffstat (limited to 'arch/avr32')
-rw-r--r--arch/avr32/Kconfig6
1 files changed, 3 insertions, 3 deletions
diff --git a/arch/avr32/Kconfig b/arch/avr32/Kconfig
index 05fe3053dca..414a8ad97f5 100644
--- a/arch/avr32/Kconfig
+++ b/arch/avr32/Kconfig
@@ -127,13 +127,13 @@ config BOARD_HAMMERHEAD
select CPU_AT32AP7000
select USB_ARCH_HAS_HCD
help
- The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel.
+ The Hammerhead platform is built around an AVR32 32-bit microcontroller from Atmel.
It offers versatile peripherals, such as ethernet, usb device, usb host etc.
- The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered
+ The board also incorporates a power supply and is a Power over Ethernet (PoE) Powered
Device (PD).
- Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is
+ Additionally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is
mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which
will cover even the most exceptional need of memory bandwidth. Together with the onboard
video decoder the board is ready for video processing.