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| author | Alex Deucher <alexdeucher@gmail.com> | 2009-10-27 11:16:09 -0400 |
|---|---|---|
| committer | Dave Airlie <airlied@redhat.com> | 2009-10-28 13:34:18 +1000 |
| commit | 8f552a66a40bcc6e903e91310f42fe140e0342c4 (patch) | |
| tree | 333324852853075bbcdd0962f7567e82a42ec1dc | |
| parent | 3e5cb98dfe87cc61d0a1119dd8aa2b1e4cfab424 (diff) | |
| download | kernel-crypto-8f552a66a40bcc6e903e91310f42fe140e0342c4.tar.gz kernel-crypto-8f552a66a40bcc6e903e91310f42fe140e0342c4.tar.xz kernel-crypto-8f552a66a40bcc6e903e91310f42fe140e0342c4.zip | |
drm/radeon/kms/atom: loosen pll min output limits
Limiting the pll output range is a good thing generally as
it limits the number of possible pll combinations for a given
frequency presumably to the ones that work best on each card.
That's why the limits are in the bios tables. However, certain
duallink DVI monitors seem to like pll combinations that would
be limited by this at least on pre-DCE 3.0 r6xx hardware. This
might need to be adjusted per family or per clock range in the
future.
See fdo bug 24727.
Signed-off-by: Alex Deucher <alexdeucher@gmail.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
| -rw-r--r-- | drivers/gpu/drm/radeon/radeon_atombios.c | 10 |
1 files changed, 10 insertions, 0 deletions
diff --git a/drivers/gpu/drm/radeon/radeon_atombios.c b/drivers/gpu/drm/radeon/radeon_atombios.c index 18729259c2f..1c9a9c46176 100644 --- a/drivers/gpu/drm/radeon/radeon_atombios.c +++ b/drivers/gpu/drm/radeon/radeon_atombios.c @@ -655,6 +655,16 @@ bool radeon_atom_get_clock_info(struct drm_device *dev) p1pll->pll_out_min = 64800; else p1pll->pll_out_min = 20000; + } else if (p1pll->pll_out_min > 64800) { + /* Limiting the pll output range is a good thing generally as + * it limits the number of possible pll combinations for a given + * frequency presumably to the ones that work best on each card. + * However, certain duallink DVI monitors seem to like + * pll combinations that would be limited by this at least on + * pre-DCE 3.0 r6xx hardware. This might need to be adjusted per + * family. + */ + p1pll->pll_out_min = 64800; } p1pll->pll_in_min = |