diff options
Diffstat (limited to '0028-ARM-HYP-non-sec-add-a-barrier-after-setting-SCR.NS-1.patch')
-rw-r--r-- | 0028-ARM-HYP-non-sec-add-a-barrier-after-setting-SCR.NS-1.patch | 28 |
1 files changed, 28 insertions, 0 deletions
diff --git a/0028-ARM-HYP-non-sec-add-a-barrier-after-setting-SCR.NS-1.patch b/0028-ARM-HYP-non-sec-add-a-barrier-after-setting-SCR.NS-1.patch new file mode 100644 index 0000000..f282a7b --- /dev/null +++ b/0028-ARM-HYP-non-sec-add-a-barrier-after-setting-SCR.NS-1.patch @@ -0,0 +1,28 @@ +From ffddd794d834f39e120603d6764d7f25bf24ddc0 Mon Sep 17 00:00:00 2001 +From: Marc Zyngier <marc.zyngier@arm.com> +Date: Sat, 26 Apr 2014 13:17:03 +0100 +Subject: [PATCH 28/36] ARM: HYP/non-sec: add a barrier after setting SCR.NS==1 + +A CP15 instruction execution can be reordered, requiring an +isb to be sure it is executed in program order. + +Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> +--- + arch/arm/cpu/armv7/nonsec_virt.S | 1 + + 1 file changed, 1 insertion(+) + +diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S +index 6367e09..12de5c2 100644 +--- a/arch/arm/cpu/armv7/nonsec_virt.S ++++ b/arch/arm/cpu/armv7/nonsec_virt.S +@@ -46,6 +46,7 @@ _secure_monitor: + #endif + + mcr p15, 0, r1, c1, c1, 0 @ write SCR (with NS bit set) ++ isb + + #ifdef CONFIG_ARMV7_VIRT + mrceq p15, 0, r0, c12, c0, 1 @ get MVBAR value +-- +1.9.0 + |