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authorDennis Gilmore <dennis@ausil.us>2014-04-26 21:49:55 -0500
committerDennis Gilmore <dennis@ausil.us>2014-04-26 21:49:55 -0500
commit1619496436087ded318042cbc8c1a5b0513c2b7f (patch)
tree111d7e2d85a06de381d91c66d971a70d53302db8 /0034-ARM-HYP-non-sec-add-the-option-for-a-second-stage-mo.patch
parent0454bb3cbb683f2e5f15d473893ea6645cbc1293 (diff)
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add cubietruck u-boot image
Diffstat (limited to '0034-ARM-HYP-non-sec-add-the-option-for-a-second-stage-mo.patch')
-rw-r--r--0034-ARM-HYP-non-sec-add-the-option-for-a-second-stage-mo.patch47
1 files changed, 47 insertions, 0 deletions
diff --git a/0034-ARM-HYP-non-sec-add-the-option-for-a-second-stage-mo.patch b/0034-ARM-HYP-non-sec-add-the-option-for-a-second-stage-mo.patch
new file mode 100644
index 0000000..291a570
--- /dev/null
+++ b/0034-ARM-HYP-non-sec-add-the-option-for-a-second-stage-mo.patch
@@ -0,0 +1,47 @@
+From e9b55c2e26b83bffe6dea6ea4be8fbc249bb85d5 Mon Sep 17 00:00:00 2001
+From: Marc Zyngier <marc.zyngier@arm.com>
+Date: Sat, 26 Apr 2014 13:17:09 +0100
+Subject: [PATCH 34/36] ARM: HYP/non-sec: add the option for a second-stage
+ monitor
+
+Allow the switch to a second stage secure monitor just before
+switching to non-secure.
+
+This allows a resident piece of firmware to be active once the
+kernel has been entered (the u-boot monitor is dead anyway,
+its pages being reused).
+
+Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
+---
+ arch/arm/cpu/armv7/nonsec_virt.S | 13 +++++++++++--
+ 1 file changed, 11 insertions(+), 2 deletions(-)
+
+diff --git a/arch/arm/cpu/armv7/nonsec_virt.S b/arch/arm/cpu/armv7/nonsec_virt.S
+index 2a43e3c..745670e 100644
+--- a/arch/arm/cpu/armv7/nonsec_virt.S
++++ b/arch/arm/cpu/armv7/nonsec_virt.S
+@@ -44,10 +44,19 @@ _monitor_vectors:
+ * ip: target PC
+ */
+ _secure_monitor:
++#ifdef CONFIG_ARMV7_PSCI
++ ldr r5, =_psci_vectors @ Switch to the next monitor
++ mcr p15, 0, r5, c12, c0, 1
++ isb
++
++ @ Obtain a secure stack, and configure the PSCI backend
++ bl psci_arch_init
++#endif
++
+ mrc p15, 0, r5, c1, c1, 0 @ read SCR
+- bic r5, r5, #0x4e @ clear IRQ, FIQ, EA, nET bits
++ bic r5, r5, #0x4a @ clear IRQ, EA, nET bits
+ orr r5, r5, #0x31 @ enable NS, AW, FW bits
+-
++ @ FIQ preserved for secure mode
+ mov r6, #SVC_MODE @ default mode is SVC
+ is_cpu_virt_capable r4
+ #ifdef CONFIG_ARMV7_VIRT
+--
+1.9.0
+