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Mode	Name	Size
-rw-r--r--	README	1732	log stats plain
-rw-r--r--	biorhythm.rb	4362	log stats plain
-rw-r--r--	cal.rb	3336	log stats plain
-rw-r--r--	cbreak.rb	564	log stats plain
-rw-r--r--	clnt.rb	404	log stats plain
-rw-r--r--	dbmtest.rb	235	log stats plain
-rw-r--r--	dir.rb	185	log stats plain
d---------	drb	1656	log stats plain
-rw-r--r--	dualstack-fetch.rb	1044	log stats plain
-rw-r--r--	dualstack-httpd.rb	1453	log stats plain
-rw-r--r--	eval.rb	719	log stats plain
-rw-r--r--	export.rb	419	log stats plain
-rw-r--r--	exyacc.rb	542	log stats plain
-rw-r--r--	fact.rb	125	log stats plain
-rw-r--r--	fib.awk	115	log stats plain
-rw-r--r--	fib.pl	129	log stats plain
-rw-r--r--	fib.py	130	log stats plain
-rw-r--r--	fib.rb	129	log stats plain
-rw-r--r--	fib.scm	115	log stats plain
-rw-r--r--	freq.rb	225	log stats plain
-rw-r--r--	from.rb	1737	log stats plain
-rw-r--r--	fullpath.rb	350	log stats plain
-rw-r--r--	getopts.test	665	log stats plain
-rw-r--r--	goodfriday.rb	1286	log stats plain
-rw-r--r--	less.rb	414	log stats plain
-rw-r--r--	list.rb	1416	log stats plain
-rw-r--r--	list2.rb	336	log stats plain
-rw-r--r--	list3.rb	345	log stats plain
d---------	logger	107	log stats plain
-rw-r--r--	mine.rb	3995	log stats plain
-rw-r--r--	mkproto.rb	594	log stats plain
-rw-r--r--	mpart.rb	755	log stats plain
-rw-r--r--	mrshtest.rb	235	log stats plain
-rw-r--r--	observ.rb	470	log stats plain
-rw-r--r--	occur.pl	118	log stats plain
-rw-r--r--	occur.rb	217	log stats plain
-rw-r--r--	occur2.rb	272	log stats plain
d---------	openssl	475	log stats plain
d---------	optparse	79	log stats plain
-rw-r--r--	philos.rb	767	log stats plain
-rw-r--r--	pi.rb	323	log stats plain
-rw-r--r--	rcs.awk	638	log stats plain
-rw-r--r--	rcs.dat	595	log stats plain
-rw-r--r--	rcs.rb	923	log stats plain
-rw-r--r--	regx.rb	320	log stats plain
d---------	rss	164	log stats plain
-rw-r--r--	sieve.rb	245	log stats plain
d---------	soap	484	log stats plain
-rw-r--r--	svr.rb	495	log stats plain
-rw-r--r--	test.rb	47162	log stats plain
d---------	testunit	202	log stats plain
-rw-r--r--	time.rb	208	log stats plain
-rw-r--r--	trojan.rb	341	log stats plain
-rw-r--r--	tsvr.rb	352	log stats plain
-rw-r--r--	uumerge.rb	838	log stats plain
d---------	webrick	361	log stats plain
d---------	wsdl	135	log stats plain

span class="hl opt">; unsigned int ddr_sdram_mode_10; unsigned int ddr_sdram_mode_11; unsigned int ddr_sdram_mode_12; unsigned int ddr_sdram_mode_13; unsigned int ddr_sdram_mode_14; unsigned int ddr_sdram_mode_15; unsigned int ddr_sdram_mode_16; unsigned int ddr_sdram_md_cntl; unsigned int ddr_sdram_interval; unsigned int ddr_data_init; unsigned int ddr_sdram_clk_cntl; unsigned int ddr_init_addr; unsigned int ddr_init_ext_addr; unsigned int timing_cfg_4; unsigned int timing_cfg_5; unsigned int timing_cfg_6; unsigned int timing_cfg_7; unsigned int timing_cfg_8; unsigned int timing_cfg_9; unsigned int ddr_zq_cntl; unsigned int ddr_wrlvl_cntl; unsigned int ddr_wrlvl_cntl_2; unsigned int ddr_wrlvl_cntl_3; unsigned int ddr_sr_cntr; unsigned int ddr_sdram_rcw_1; unsigned int ddr_sdram_rcw_2; unsigned int ddr_sdram_rcw_3; unsigned int ddr_sdram_rcw_4; unsigned int ddr_sdram_rcw_5; unsigned int ddr_sdram_rcw_6; unsigned int dq_map_0; unsigned int dq_map_1; unsigned int dq_map_2; unsigned int dq_map_3; unsigned int ddr_eor; unsigned int ddr_cdr1; unsigned int ddr_cdr2; unsigned int err_disable; unsigned int err_int_en; unsigned int debug[64]; } fsl_ddr_cfg_regs_t; typedef struct memctl_options_partial_s { unsigned int all_dimms_ecc_capable; unsigned int all_dimms_tckmax_ps; unsigned int all_dimms_burst_lengths_bitmask; unsigned int all_dimms_registered; unsigned int all_dimms_unbuffered; /* unsigned int lowest_common_spd_caslat; */ unsigned int all_dimms_minimum_trcd_ps; } memctl_options_partial_t; #define DDR_DATA_BUS_WIDTH_64 0 #define DDR_DATA_BUS_WIDTH_32 1 #define DDR_DATA_BUS_WIDTH_16 2 #define DDR_CSWL_CS0 0x04000001 /* * Generalized parameters for memory controller configuration, * might be a little specific to the FSL memory controller */ typedef struct memctl_options_s { /* * Memory organization parameters * * if DIMM is present in the system * where DIMMs are with respect to chip select * where chip selects are with respect to memory boundaries */ unsigned int registered_dimm_en; /* use registered DIMM support */ /* Options local to a Chip Select */ struct cs_local_opts_s { unsigned int auto_precharge; unsigned int odt_rd_cfg; unsigned int odt_wr_cfg; unsigned int odt_rtt_norm; unsigned int odt_rtt_wr; } cs_local_opts[CONFIG_CHIP_SELECTS_PER_CTRL]; /* Special configurations for chip select */ unsigned int memctl_interleaving; unsigned int memctl_interleaving_mode; unsigned int ba_intlv_ctl; unsigned int addr_hash; /* Operational mode parameters */ unsigned int ecc_mode; /* Use ECC? */ /* Initialize ECC using memory controller? */ unsigned int ecc_init_using_memctl; unsigned int dqs_config; /* Use DQS? maybe only with DDR2? */ /* SREN - self-refresh during sleep */ unsigned int self_refresh_in_sleep; /* SR_IE - Self-refresh interrupt enable */ unsigned int self_refresh_interrupt_en; unsigned int dynamic_power; /* DYN_PWR */ /* memory data width to use (16-bit, 32-bit, 64-bit) */ unsigned int data_bus_width; unsigned int burst_length; /* BL4, OTF and BL8 */ /* On-The-Fly Burst Chop enable */ unsigned int otf_burst_chop_en; /* mirrior DIMMs for DDR3 */ unsigned int mirrored_dimm; unsigned int quad_rank_present; unsigned int ap_en; /* address parity enable for RDIMM/DDR4-UDIMM */ unsigned int x4_en; /* enable x4 devices */ unsigned int package_3ds; /* Global Timing Parameters */ unsigned int cas_latency_override; unsigned int cas_latency_override_value; unsigned int use_derated_caslat; unsigned int additive_latency_override; unsigned int additive_latency_override_value; unsigned int clk_adjust; /* */ unsigned int cpo_override; /* override timing_cfg_2[CPO]*/ unsigned int cpo_sample; /* optimize debug_29[24:31] */ unsigned int write_data_delay; /* DQS adjust */ unsigned int cswl_override; unsigned int wrlvl_override; unsigned int wrlvl_sample; /* Write leveling */ unsigned int wrlvl_start; unsigned int wrlvl_ctl_2; unsigned int wrlvl_ctl_3; unsigned int half_strength_driver_enable; unsigned int twot_en; unsigned int threet_en; unsigned int bstopre; unsigned int tfaw_window_four_activates_ps; /* tFAW -- FOUR_ACT */ /* Rtt impedance */ unsigned int rtt_override; /* rtt_override enable */ unsigned int rtt_override_value; /* that is Rtt_Nom for DDR3 */ unsigned int rtt_wr_override_value; /* this is Rtt_WR for DDR3 */ /* Automatic self refresh */ unsigned int auto_self_refresh_en; unsigned int sr_it; /* ZQ calibration */ unsigned int zq_en; /* Write leveling */ unsigned int wrlvl_en; /* RCW override for RDIMM */ unsigned int rcw_override; unsigned int rcw_1; unsigned int rcw_2; unsigned int rcw_3; /* control register 1 */ unsigned int ddr_cdr1; unsigned int ddr_cdr2; unsigned int trwt_override; unsigned int trwt; /* read-to-write turnaround */ } memctl_options_t; phys_size_t fsl_ddr_sdram(void); phys_size_t fsl_ddr_sdram_size(void); phys_size_t fsl_other_ddr_sdram(unsigned long long base, unsigned int first_ctrl, unsigned int num_ctrls, unsigned int dimm_slots_per_ctrl, int (*board_need_reset)(void), void (*board_reset)(void), void (*board_de_reset)(void)); extern int fsl_use_spd(void); void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, unsigned int ctrl_num, int step); u32 fsl_ddr_get_intl3r(void); void print_ddr_info(unsigned int start_ctrl); static void __board_assert_mem_reset(void) { } static void __board_deassert_mem_reset(void) { } void board_assert_mem_reset(void) __attribute__((weak, alias("__board_assert_mem_reset"))); void board_deassert_mem_reset(void) __attribute__((weak, alias("__board_deassert_mem_reset"))); static int __board_need_mem_reset(void) { return 0; } int board_need_mem_reset(void) __attribute__((weak, alias("__board_need_mem_reset"))); #if defined(CONFIG_DEEP_SLEEP) void board_mem_sleep_setup(void); bool is_warm_boot(void); int fsl_dp_resume(void); #endif /* * The 85xx boards have a common prototype for fixed_sdram so put the * declaration here. */ #ifdef CONFIG_MPC85xx extern phys_size_t fixed_sdram(void); #endif #if defined(CONFIG_DDR_ECC) extern void ddr_enable_ecc(unsigned int dram_size); #endif typedef struct fixed_ddr_parm{ int min_freq; int max_freq; fsl_ddr_cfg_regs_t *ddr_settings; } fixed_ddr_parm_t; /** * fsl_initdram() - Set up the SDRAM * * @return 0 if OK, -ve on error */ int fsl_initdram(void); #endif