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/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2009-2011 Freescale Semiconductor, Inc. */ #ifndef __DTSEC_H__ #define __DTSEC_H__ #include <asm/types.h> struct dtsec { u32 tsec_id; /* controller ID and version */ u32 tsec_id2; /* controller ID and configuration */ u32 ievent; /* interrupt event */ u32 imask; /* interrupt mask */ u32 res0; u32 ecntrl; /* ethernet control and configuration */ u32 ptv; /* pause time value */ u32 tbipa; /* TBI PHY address */ u32 res1[8]; u32 tctrl; /* Transmit control register */ u32 res2[3]; u32 rctrl; /* Receive control register */ u32 res3[11]; u32 igaddr[8]; /* Individual group address */ u32 gaddr[8]; /* group address */ u32 res4[16]; u32 maccfg1; /* MAC configuration register 1 */ u32 maccfg2; /* MAC configuration register 2 */ u32 ipgifg; /* inter-packet/inter-frame gap */ u32 hafdup; /* half-duplex control */ u32 maxfrm; /* Maximum frame size */ u32 res5[3]; u32 miimcfg; /* MII management configuration */ u32 miimcom; /* MII management command */ u32 miimadd; /* MII management address */ u32 miimcon; /* MII management control */ u32 miimstat; /* MII management status */ u32 miimind; /* MII management indicator */ u32 res6; u32 ifstat; /* Interface status */ u32 macstnaddr1; /* MAC station address 1 */ u32 macstnaddr2; /* MAC station address 2 */ u32 res7[46]; /* transmit and receive counter */ u32 tr64; /* Tx and Rx 64 bytes frame */ u32 tr127; /* Tx and Rx 65 to 127 bytes frame */ u32 tr255; /* Tx and Rx 128 to 255 bytes frame */ u32 tr511; /* Tx and Rx 256 to 511 bytes frame */ u32 tr1k; /* Tx and Rx 512 to 1023 bytes frame */ u32 trmax; /* Tx and Rx 1024 to 1518 bytes frame */ u32 trmgv; /* Tx and Rx 1519 to 1522 good VLAN frame */ /* receive counters */ u32 rbyt; /* Receive byte counter */ u32 rpkt; /* Receive packet counter */ u32 rfcs; /* Receive FCS error */ u32 rmca; /* Receive multicast packet */ u32 rbca; /* Receive broadcast packet */ u32 rxcf; /* Receive control frame */ u32 rxpf; /* Receive pause frame */ u32 rxuo; /* Receive unknown OP code */ u32 raln; /* Receive alignment error */ u32 rflr; /* Receive frame length error */ u32 rcde; /* Receive code error */ u32 rcse; /* Receive carrier sense error */ u32 rund; /* Receive undersize packet */ u32 rovr; /* Receive oversize packet */ u32 rfrg; /* Receive fragments counter */ u32 rjbr; /* Receive jabber counter */ u32 rdrp; /* Receive drop counter */ /* transmit counters */ u32 tbyt; /* Transmit byte counter */ u32 tpkt; /* Transmit packet */ u32 tmca; /* Transmit multicast packet */ u32 tbca; /* Transmit broadcast packet */ u32 txpf; /* Transmit pause control frame */ u32 tdfr; /* Transmit deferral packet */ u32 tedf; /* Transmit excessive deferral pkt */ u32 tscl; /* Transmit single collision pkt */ u32 tmcl; /* Transmit multiple collision pkt */ u32 tlcl; /* Transmit late collision pkt */ u32 txcl; /* Transmit excessive collision */ u32 tncl; /* Transmit total collision */ u32 res8; u32 tdrp; /* Transmit drop frame */ u32 tjbr; /* Transmit jabber frame */ u32 tfcs; /* Transmit FCS error */ u32 txcf; /* Transmit control frame */ u32 tovr; /* Transmit oversize frame */ u32 tund; /* Transmit undersize frame */ u32 tfrg; /* Transmit fragments frame */ /* counter controls */ u32 car1; /* carry register 1 */ u32 car2; /* carry register 2 */ u32 cam1; /* carry register 1 mask */ u32 cam2; /* carry register 2 mask */ u32 res9[80]; }; /* TBI register addresses */ #define TBI_CR 0x00 #define TBI_SR 0x01 #define TBI_ANA 0x04 #define TBI_ANLPBPA 0x05 #define TBI_ANEX 0x06 #define TBI_TBICON 0x11 /* TBI MDIO register bit fields*/ #define TBICON_CLK_SELECT 0x0020 #define TBIANA_ASYMMETRIC_PAUSE 0x0100 #define TBIANA_SYMMETRIC_PAUSE 0x0080 #define TBIANA_HALF_DUPLEX 0x0040 #define TBIANA_FULL_DUPLEX 0x0020 #define TBICR_PHY_RESET 0x8000 #define TBICR_ANEG_ENABLE 0x1000 #define TBICR_RESTART_ANEG 0x0200 #define TBICR_FULL_DUPLEX 0x0100 #define TBICR_SPEED1_SET 0x0040 /* IEVENT - interrupt events register */ #define IEVENT_BABR 0x80000000 /* Babbling receive error */ #define IEVENT_RXC 0x40000000 /* pause control frame received */ #define IEVENT_MSRO 0x04000000 /* MIB counter overflow */ #define IEVENT_GTSC 0x02000000 /* Graceful transmit stop complete */ #define IEVENT_BABT 0x01000000 /* Babbling transmit error */ #define IEVENT_TXC 0x00800000 /* control frame transmitted */ #define IEVENT_TXE 0x00400000 /* Transmit channel error */ #define IEVENT_LC 0x00040000 /* Late collision occurred */ #define IEVENT_CRL 0x00020000 /* Collision retry exceed limit */ #define IEVENT_XFUN 0x00010000 /* Transmit FIFO underrun */ #define IEVENT_ABRT 0x00008000 /* Transmit packet abort */ #define IEVENT_MMRD 0x00000400 /* MII management read complete */


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