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author	matz <matz@b2dd03c8-39d4-4d8f-98ff-823fe69b080e>	2005-12-24 09:58:57 +0000
committer	matz <matz@b2dd03c8-39d4-4d8f-98ff-823fe69b080e>	2005-12-24 09:58:57 +0000
commit	9422e45a216c6914b961a7082afff6aa71851bd9 (patch)
tree	4c21b83a72c9e6262dc58b4c09454c57c7c52a67 /lib/xsd/codegen/classdef.rb
parent	c9f612c04a4f9e6379aa6466785e9e67fd5a5e79 (diff)
download	ruby-9422e45a216c6914b961a7082afff6aa71851bd9.tar.gz ruby-9422e45a216c6914b961a7082afff6aa71851bd9.tar.xz ruby-9422e45a216c6914b961a7082afff6aa71851bd9.zip

* stable version 1.8.4 released.

* ext/digest/sha2/sha2.c (ULL): support AIX C. a patch from Kailden <kailden at gmail.com>. [ruby-core:06984] git-svn-id: http://svn.ruby-lang.org/repos/ruby/branches/ruby_1_8@9734 b2dd03c8-39d4-4d8f-98ff-823fe69b080e

Diffstat (limited to 'lib/xsd/codegen/classdef.rb')

0 files changed, 0 insertions, 0 deletions

/* * Dave Ethernet Controller driver * * Copyright (C) 2008 Dave S.r.l. <www.dave.eu> * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License version 2 as * published by the Free Software Foundation. */ #include <common.h> #include <log.h> #include <linux/delay.h> #ifndef CONFIG_DNET_AUTONEG_TIMEOUT #define CONFIG_DNET_AUTONEG_TIMEOUT 5000000 /* default value */ #endif #include <net.h> #include <malloc.h> #include <linux/mii.h> #include <miiphy.h> #include <asm/io.h> #include <asm/unaligned.h> #include "dnet.h" struct dnet_device { struct dnet_registers *regs; const struct device *dev; struct eth_device netdev; unsigned short phy_addr; }; /* get struct dnet_device from given struct netdev */ #define to_dnet(_nd) container_of(_nd, struct dnet_device, netdev) /* function for reading internal MAC register */ u16 dnet_readw_mac(struct dnet_device *dnet, u16 reg) { u16 data_read; /* issue a read */ writel(reg, &dnet->regs->MACREG_ADDR); /* since a read/write op to the MAC is very slow, * we must wait before reading the data */ udelay(1); /* read data read from the MAC register */ data_read = readl(&dnet->regs->MACREG_DATA); /* all done */ return data_read; } /* function for writing internal MAC register */ void dnet_writew_mac(struct dnet_device *dnet, u16 reg, u16 val) { /* load data to write */ writel(val, &dnet->regs->MACREG_DATA); /* issue a write */ writel(reg | DNET_INTERNAL_WRITE, &dnet->regs->MACREG_ADDR); /* since a read/write op to the MAC is very slow, * we must wait before exiting */ udelay(1); } static void dnet_mdio_write(struct dnet_device *dnet, u8 reg, u16 value) { u16 tmp; debug(DRIVERNAME "dnet_mdio_write %02x:%02x <- %04x\n", dnet->phy_addr, reg, value); while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) & DNET_INTERNAL_GMII_MNG_CMD_FIN)) ; /* prepare for a write operation */ tmp = (1 << 13); /* only 5 bits allowed for register offset */ reg &= 0x1f; /* prepare reg_value for a write */ tmp |= (dnet->phy_addr << 8); tmp |= reg; /* write data to write first */ dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG, value); /* write control word */ dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, tmp); while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) & DNET_INTERNAL_GMII_MNG_CMD_FIN)) ; } static u16 dnet_mdio_read(struct dnet_device *dnet, u8 reg) { u16 value; while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) & DNET_INTERNAL_GMII_MNG_CMD_FIN)) ; /* only 5 bits allowed for register offset*/ reg &= 0x1f; /* prepare reg_value for a read */ value = (dnet->phy_addr << 8); value |= reg; /* write control word */ dnet_writew_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG, value); /* wait for end of transfer */ while (!(dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_CTL_REG) & DNET_INTERNAL_GMII_MNG_CMD_FIN)) ; value = dnet_readw_mac(dnet, DNET_INTERNAL_GMII_MNG_DAT_REG); debug(DRIVERNAME "dnet_mdio_read %02x:%02x <- %04x\n", dnet->phy_addr, reg, value); return value; } static int dnet_send(struct eth_device *netdev, void *packet, int length) { struct dnet_device *dnet = to_dnet(netdev); int i, wrsz; unsigned int *bufp; unsigned int tx_cmd; debug(DRIVERNAME "[%s] Sending %u bytes\n", __func__, length); bufp = (unsigned int *) (((u32)packet) & 0xFFFFFFFC); wrsz = (u32)length + 3; wrsz += ((u32)packet) & 0x3; wrsz >>= 2; tx_cmd = ((((unsigned int)(packet)) & 0x03) << 16) | (u32)length; /* check if there is enough room for the current frame */ if (wrsz < (DNET_FIFO_SIZE - readl(&dnet->regs->TX_FIFO_WCNT))) { for (i = 0; i < wrsz; i++) writel(*bufp++, &dnet->regs->TX_DATA_FIFO); /* * inform MAC that a packet's written and ready * to be shipped out */ writel(tx_cmd, &dnet->regs->TX_LEN_FIFO); } else { printf(DRIVERNAME "No free space (actual %d, required %d " "(words))\n", DNET_FIFO_SIZE - readl(&dnet->regs->TX_FIFO_WCNT), wrsz); } /* No one cares anyway */ return 0; } static int dnet_recv(struct eth_device *netdev) { struct dnet_device *dnet = to_dnet(netdev); unsigned int *data_ptr; int pkt_len, poll, i; u32 cmd_word; debug("Waiting for pkt (polling)\n"); poll = 50; while ((readl(&dnet->regs->RX_FIFO_WCNT) >> 16) == 0) { udelay(10); /* wait 10 usec */ if (--poll == 0) return 0; /* no pkt available */ } cmd_word = readl(&dnet->regs->RX_LEN_FIFO); pkt_len = cmd_word & 0xFFFF; debug("Got pkt with size %d bytes\n", pkt_len); if (cmd_word & 0xDF180000) printf("%s packet receive error %x\n", __func__, cmd_word); data_ptr = (unsigned int *)net_rx_packets[0]; for (i = 0; i < (pkt_len + 3) >> 2; i++) *data_ptr++ = readl(&dnet->regs->RX_DATA_FIFO); /* ok + 5 ?? */ net_process_received_packet(net_rx_packets[0], pkt_len + 5); return 0; }


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