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author	nobu <nobu@b2dd03c8-39d4-4d8f-98ff-823fe69b080e>	2006-10-03 23:53:14 +0000
committer	nobu <nobu@b2dd03c8-39d4-4d8f-98ff-823fe69b080e>	2006-10-03 23:53:14 +0000
commit	39363f0c8fa4cb7a52e9c1d2a90af9809fabdd7a (patch)
tree	44dff7e16771be366484cbd3526f12eab42526b0 /lib/test/unit
parent	2fab67bd30ab3375104997f159594e47a9bd3f9e (diff)
download	ruby-39363f0c8fa4cb7a52e9c1d2a90af9809fabdd7a.tar.gz ruby-39363f0c8fa4cb7a52e9c1d2a90af9809fabdd7a.tar.xz ruby-39363f0c8fa4cb7a52e9c1d2a90af9809fabdd7a.zip

2006-10-04

git-svn-id: http://svn.ruby-lang.org/repos/ruby/branches/ruby_1_8@11076 b2dd03c8-39d4-4d8f-98ff-823fe69b080e

Diffstat (limited to 'lib/test/unit')

0 files changed, 0 insertions, 0 deletions

/* * (C) Copyright 2003 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * This file is based on mpc4200fec.h * (C) Copyright Motorola, Inc., 2000 * * odin ethernet header file */ #ifndef __MPC5XXX_FEC_H #define __MPC5XXX_FEC_H typedef unsigned long uint32; typedef unsigned short uint16; typedef unsigned char uint8; typedef struct ethernet_register_set { /* [10:2]addr = 00 */ /* Control and status Registers (offset 000-1FF) */ volatile uint32 fec_id; /* MBAR_ETH + 0x000 */ volatile uint32 ievent; /* MBAR_ETH + 0x004 */ volatile uint32 imask; /* MBAR_ETH + 0x008 */ volatile uint32 RES0[1]; /* MBAR_ETH + 0x00C */ volatile uint32 r_des_active; /* MBAR_ETH + 0x010 */ volatile uint32 x_des_active; /* MBAR_ETH + 0x014 */ volatile uint32 r_des_active_cl; /* MBAR_ETH + 0x018 */ volatile uint32 x_des_active_cl; /* MBAR_ETH + 0x01C */ volatile uint32 ivent_set; /* MBAR_ETH + 0x020 */ volatile uint32 ecntrl; /* MBAR_ETH + 0x024 */ volatile uint32 RES1[6]; /* MBAR_ETH + 0x028-03C */ volatile uint32 mii_data; /* MBAR_ETH + 0x040 */ volatile uint32 mii_speed; /* MBAR_ETH + 0x044 */ volatile uint32 mii_status; /* MBAR_ETH + 0x048 */ volatile uint32 RES2[5]; /* MBAR_ETH + 0x04C-05C */ volatile uint32 mib_data; /* MBAR_ETH + 0x060 */ volatile uint32 mib_control; /* MBAR_ETH + 0x064 */ volatile uint32 RES3[6]; /* MBAR_ETH + 0x068-7C */ volatile uint32 r_activate; /* MBAR_ETH + 0x080 */ volatile uint32 r_cntrl; /* MBAR_ETH + 0x084 */ volatile uint32 r_hash; /* MBAR_ETH + 0x088 */ volatile uint32 r_data; /* MBAR_ETH + 0x08C */ volatile uint32 ar_done; /* MBAR_ETH + 0x090 */ volatile uint32 r_test; /* MBAR_ETH + 0x094 */ volatile uint32 r_mib; /* MBAR_ETH + 0x098 */ volatile uint32 r_da_low; /* MBAR_ETH + 0x09C */ volatile uint32 r_da_high; /* MBAR_ETH + 0x0A0 */ volatile uint32 RES4[7]; /* MBAR_ETH + 0x0A4-0BC */ volatile uint32 x_activate; /* MBAR_ETH + 0x0C0 */ volatile uint32 x_cntrl; /* MBAR_ETH + 0x0C4 */ volatile uint32 backoff; /* MBAR_ETH + 0x0C8 */ volatile uint32 x_data; /* MBAR_ETH + 0x0CC */ volatile uint32 x_status; /* MBAR_ETH + 0x0D0 */ volatile uint32 x_mib; /* MBAR_ETH + 0x0D4 */ volatile uint32 x_test; /* MBAR_ETH + 0x0D8 */ volatile uint32 fdxfc_da1; /* MBAR_ETH + 0x0DC */ volatile uint32 fdxfc_da2; /* MBAR_ETH + 0x0E0 */ volatile uint32 paddr1; /* MBAR_ETH + 0x0E4 */ volatile uint32 paddr2; /* MBAR_ETH + 0x0E8 */ volatile uint32 op_pause; /* MBAR_ETH + 0x0EC */ volatile uint32 RES5[4]; /* MBAR_ETH + 0x0F0-0FC */ volatile uint32 instr_reg; /* MBAR_ETH + 0x100 */ volatile uint32 context_reg; /* MBAR_ETH + 0x104 */ volatile uint32 test_cntrl; /* MBAR_ETH + 0x108 */ volatile uint32 acc_reg; /* MBAR_ETH + 0x10C */


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