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author	usa <usa@b2dd03c8-39d4-4d8f-98ff-823fe69b080e>	2005-08-31 02:37:15 +0000
committer	usa <usa@b2dd03c8-39d4-4d8f-98ff-823fe69b080e>	2005-08-31 02:37:15 +0000
commit	711f71b76122400b27980df5a225beadbef22ac2 (patch)
tree	a386b2daed4c48c1cb5e0f323d74c9c339d34324 /ext/tk/sample/multi-ip_sample2.rb
parent	e7fb308be526def9536e10c00751772bea91ad4f (diff)
download	ruby-711f71b76122400b27980df5a225beadbef22ac2.tar.gz ruby-711f71b76122400b27980df5a225beadbef22ac2.tar.xz ruby-711f71b76122400b27980df5a225beadbef22ac2.zip

* test/gdbm/test_gdbm.rb (teardown): should remove GDBM temporary

file. git-svn-id: http://svn.ruby-lang.org/repos/ruby/branches/ruby_1_8@9059 b2dd03c8-39d4-4d8f-98ff-823fe69b080e

Diffstat (limited to 'ext/tk/sample/multi-ip_sample2.rb')

0 files changed, 0 insertions, 0 deletions

// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2016 Freescale Semiconductor, Inc. * Copyright 2017 NXP */ /dts-v1/; /* First 128KB is for PSCI ATF. */ /memreserve/ 0x80000000 0x00020000; #include "fsl-imx8qm.dtsi" / { model = "Advantech iMX8QM Qseven series"; compatible = "fsl,imx8qm-mek", "fsl,imx8qm"; chosen { bootargs = "console=ttyLP0,115200 earlycon=lpuart32,0x5a060000,115200"; stdout-path = &lpuart0; }; leds { compatible = "gpio-leds"; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpio_leds>; user { label = "heartbeat"; gpios = <&gpio2 15 0>; default-state = "on"; linux,default-trigger = "heartbeat"; }; }; regulators { compatible = "simple-bus"; #address-cells = <1>; #size-cells = <0>; reg_usb_otg1_vbus: regulator@0 { compatible = "regulator-fixed"; reg = <0>; regulator-name = "usb_otg1_vbus"; regulator-min-microvolt = <5000000>; regulator-max-microvolt = <5000000>; gpio = <&gpio4 3 GPIO_ACTIVE_HIGH>; enable-active-high; }; reg_usdhc2_vmmc: usdhc2_vmmc { compatible = "regulator-fixed"; regulator-name = "sw-3p3-sd1"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; gpio = <&gpio4 7 GPIO_ACTIVE_HIGH>; enable-active-high; }; }; }; &iomuxc { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_hog_1>; imx8qm-mek { pinctrl_hog_1: hoggrp-1 { fsl,pins = < SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x06000048 >; }; pinctrl_fec1: fec1grp { fsl,pins = < SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETB_PAD 0x000014a0 SC_P_ENET0_MDC_CONN_ENET0_MDC 0x06000048 SC_P_ENET0_MDIO_CONN_ENET0_MDIO 0x06000048 SC_P_ENET0_RGMII_TX_CTL_CONN_ENET0_RGMII_TX_CTL 0x00000060 SC_P_ENET0_RGMII_TXC_CONN_ENET0_RGMII_TXC 0x00000060 SC_P_ENET0_RGMII_TXD0_CONN_ENET0_RGMII_TXD0 0x00000060 SC_P_ENET0_RGMII_TXD1_CONN_ENET0_RGMII_TXD1 0x00000060 SC_P_ENET0_RGMII_TXD2_CONN_ENET0_RGMII_TXD2 0x00000060 SC_P_ENET0_RGMII_TXD3_CONN_ENET0_RGMII_TXD3 0x00000060 SC_P_ENET0_RGMII_RXC_CONN_ENET0_RGMII_RXC 0x00000060 SC_P_ENET0_RGMII_RX_CTL_CONN_ENET0_RGMII_RX_CTL 0x00000060 SC_P_ENET0_RGMII_RXD0_CONN_ENET0_RGMII_RXD0 0x00000060 SC_P_ENET0_RGMII_RXD1_CONN_ENET0_RGMII_RXD1 0x00000060 SC_P_ENET0_RGMII_RXD2_CONN_ENET0_RGMII_RXD2 0x00000060 SC_P_ENET0_RGMII_RXD3_CONN_ENET0_RGMII_RXD3 0x00000060 >; }; pinctrl_fec2: fec2grp { fsl,pins = < SC_P_COMP_CTL_GPIO_1V8_3V3_ENET_ENETA_PAD 0x000014a0 SC_P_ENET1_RGMII_TX_CTL_CONN_ENET1_RGMII_TX_CTL 0x00000060 SC_P_ENET1_RGMII_TXC_CONN_ENET1_RGMII_TXC 0x00000060 SC_P_ENET1_RGMII_TXD0_CONN_ENET1_RGMII_TXD0 0x00000060 SC_P_ENET1_RGMII_TXD1_CONN_ENET1_RGMII_TXD1 0x00000060 SC_P_ENET1_RGMII_TXD2_CONN_ENET1_RGMII_TXD2 0x00000060 SC_P_ENET1_RGMII_TXD3_CONN_ENET1_RGMII_TXD3 0x00000060 SC_P_ENET1_RGMII_RXC_CONN_ENET1_RGMII_RXC 0x00000060 SC_P_ENET1_RGMII_RX_CTL_CONN_ENET1_RGMII_RX_CTL 0x00000060 SC_P_ENET1_RGMII_RXD0_CONN_ENET1_RGMII_RXD0 0x00000060 SC_P_ENET1_RGMII_RXD1_CONN_ENET1_RGMII_RXD1 0x00000060 SC_P_ENET1_RGMII_RXD2_CONN_ENET1_RGMII_RXD2 0x00000060 SC_P_ENET1_RGMII_RXD3_CONN_ENET1_RGMII_RXD3 0x00000060 >; }; pinctrl_lpuart0: lpuart0grp { fsl,pins = < SC_P_UART0_RX_DMA_UART0_RX 0x06000020 SC_P_UART0_TX_DMA_UART0_TX 0x06000020 >; }; pinctrl_usdhc1: usdhc1grp { fsl,pins = < SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000041 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000021 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000021 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000021 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000021 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000021 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000021 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000021 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000021 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000021 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000041 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000021 >; }; pinctrl_usdhc1_100mhz: usdhc1grp100mhz { fsl,pins = < SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 >; }; pinctrl_usdhc1_200mhz: usdhc1grp200mhz { fsl,pins = < SC_P_EMMC0_CLK_CONN_EMMC0_CLK 0x06000040 SC_P_EMMC0_CMD_CONN_EMMC0_CMD 0x00000020 SC_P_EMMC0_DATA0_CONN_EMMC0_DATA0 0x00000020 SC_P_EMMC0_DATA1_CONN_EMMC0_DATA1 0x00000020 SC_P_EMMC0_DATA2_CONN_EMMC0_DATA2 0x00000020 SC_P_EMMC0_DATA3_CONN_EMMC0_DATA3 0x00000020 SC_P_EMMC0_DATA4_CONN_EMMC0_DATA4 0x00000020 SC_P_EMMC0_DATA5_CONN_EMMC0_DATA5 0x00000020 SC_P_EMMC0_DATA6_CONN_EMMC0_DATA6 0x00000020 SC_P_EMMC0_DATA7_CONN_EMMC0_DATA7 0x00000020 SC_P_EMMC0_STROBE_CONN_EMMC0_STROBE 0x06000040 SC_P_EMMC0_RESET_B_CONN_EMMC0_RESET_B 0x00000020 >; }; pinctrl_usdhc2_gpio: usdhc2grpgpio { fsl,pins = < SC_P_USDHC1_DATA6_LSIO_GPIO5_IO21 0x00000021 SC_P_USDHC1_DATA7_LSIO_GPIO5_IO22 0x00000021 SC_P_USDHC1_RESET_B_LSIO_GPIO4_IO07 0x00000021 >; }; pinctrl_usdhc2: usdhc2grp { fsl,pins = < SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000041 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000021 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000021 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000021 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000021 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000021 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000021 >; }; pinctrl_usdhc2_100mhz: usdhc2grp100mhz { fsl,pins = < SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 >; }; pinctrl_usdhc2_200mhz: usdhc2grp200mhz { fsl,pins = < SC_P_USDHC1_CLK_CONN_USDHC1_CLK 0x06000040 SC_P_USDHC1_CMD_CONN_USDHC1_CMD 0x00000020 SC_P_USDHC1_DATA0_CONN_USDHC1_DATA0 0x00000020 SC_P_USDHC1_DATA1_CONN_USDHC1_DATA1 0x00000020 SC_P_USDHC1_DATA2_CONN_USDHC1_DATA2 0x00000020 SC_P_USDHC1_DATA3_CONN_USDHC1_DATA3 0x00000020 SC_P_USDHC1_VSELECT_CONN_USDHC1_VSELECT 0x00000020 >; }; pinctrl_usdhc3: usdhc3grp { fsl,pins = < SC_P_USDHC2_CLK_CONN_USDHC2_CLK 0x06000041 SC_P_USDHC2_CMD_CONN_USDHC2_CMD 0x00000021 SC_P_USDHC2_DATA0_CONN_USDHC2_DATA0 0x00000021 SC_P_USDHC2_DATA1_CONN_USDHC2_DATA1 0x00000021 SC_P_USDHC2_DATA2_CONN_USDHC2_DATA2 0x00000021 SC_P_USDHC2_DATA3_CONN_USDHC2_DATA3 0x00000021 /* WP */ SC_P_USDHC2_WP_LSIO_GPIO4_IO11 0x00000021 /* CD */ SC_P_USDHC2_CD_B_LSIO_GPIO4_IO12 0x00000021 >; }; pinctrl_lpi2c1: lpi2c1grp { fsl,pins = < SC_P_GPT0_CLK_DMA_I2C1_SCL 0x06000020 SC_P_GPT0_CAPTURE_DMA_I2C1_SDA 0x06000020 /* * Change the default alt function from SCL/SDA to others, * to avoid select input conflict with GPT0 */ SC_P_USB_SS3_TC0_LSIO_GPIO4_IO03 0x0700004c SC_P_USB_SS3_TC1_LSIO_GPIO4_IO04 0x0700004c SC_P_USB_SS3_TC2_LSIO_GPIO4_IO05 0x0700004c SC_P_USB_SS3_TC3_LSIO_GPIO4_IO06 0x0700004c >; }; pinctrl_gpio_leds: gpioledsgrp { fsl,pins = < SC_P_SPDIF0_TX_LSIO_GPIO2_IO15 0x00000021 >; }; }; }; &gpio2 { status = "okay"; }; &gpio4 { status = "okay"; }; &gpio5 { status = "okay"; }; &usdhc1 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc1>; pinctrl-1 = <&pinctrl_usdhc1_100mhz>; pinctrl-2 = <&pinctrl_usdhc1_200mhz>; bus-width = <8>; non-removable; status = "okay"; }; &usdhc2 { pinctrl-names = "default", "state_100mhz", "state_200mhz"; pinctrl-0 = <&pinctrl_usdhc2>, <&pinctrl_usdhc2_gpio>; pinctrl-1 = <&pinctrl_usdhc2_100mhz>, <&pinctrl_usdhc2_gpio>; pinctrl-2 = <&pinctrl_usdhc2_200mhz>, <&pinctrl_usdhc2_gpio>; bus-width = <4>; cd-gpios = <&gpio5 22 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio5 21 GPIO_ACTIVE_HIGH>; vmmc-supply = <&reg_usdhc2_vmmc>; status = "okay"; }; &usdhc3 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_usdhc3>; bus-width = <4>; cd-gpios = <&gpio4 12 GPIO_ACTIVE_LOW>; wp-gpios = <&gpio4 11 GPIO_ACTIVE_HIGH>; status = "okay"; }; &fec1 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec1>; phy-mode = "rgmii-id"; phy-handle = <&ethphy0>; fsl,ar8031-phy-fixup; fsl,magic-packet; status = "okay"; mdio { #address-cells = <1>; #size-cells = <0>; ethphy0: ethernet-phy@0 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <0>; }; ethphy1: ethernet-phy@1 { compatible = "ethernet-phy-ieee802.3-c22"; reg = <1>; }; }; }; &fec2 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_fec2>; phy-mode = "rgmii-id"; phy-handle = <&ethphy1>; fsl,ar8031-phy-fixup; fsl,magic-packet; status = "okay"; }; &i2c1 { #address-cells = <1>; #size-cells = <0>; clock-frequency = <100000>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpi2c1>; status = "okay"; pca9557_a: gpio@18 { compatible = "nxp,pca9557"; reg = <0x18>; gpio-controller; #gpio-cells = <2>; }; pca9557_b: gpio@19 { compatible = "nxp,pca9557"; reg = <0x19>; gpio-controller; #gpio-cells = <2>; }; pca9557_c: gpio@1b { compatible = "nxp,pca9557"; reg = <0x1b>; gpio-controller; #gpio-cells = <2>; }; pca9557_d: gpio@1f { compatible = "nxp,pca9557"; reg = <0x1f>; gpio-controller; #gpio-cells = <2>; }; }; &lpuart0 { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_lpuart0>; status = "okay"; }; &lpuart1 { status = "okay"; };


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