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author	ko1 <ko1@b2dd03c8-39d4-4d8f-98ff-823fe69b080e>	2008-01-03 11:26:48 +0000
committer	ko1 <ko1@b2dd03c8-39d4-4d8f-98ff-823fe69b080e>	2008-01-03 11:26:48 +0000
commit	b34ded4d206f07fd76255a16755e38765a727ffc (patch)
tree	407db6355cceb12c3323b1c6eb152d08c112a994 /ext/io/wait
parent	611f941f11bc1d97227603c069c7336e4eaf8b66 (diff)

* eval_jump.c (rb_f_catch): Resotre cfp if catched thrown object.

git-svn-id: http://svn.ruby-lang.org/repos/ruby/trunk@14870 b2dd03c8-39d4-4d8f-98ff-823fe69b080e

Diffstat (limited to 'ext/io/wait')

0 files changed, 0 insertions, 0 deletions

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/*
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#include <config.h>
#include <common.h>
#include <net.h>
#include <asm/arch/hardware.h>
#include <asm/arch/spi.h>

/*
 * Control Registers in Bank 0
 */

#define CTL_REG_ERDPTL	 0x00
#define CTL_REG_ERDPTH	 0x01
#define CTL_REG_EWRPTL	 0x02
#define CTL_REG_EWRPTH	 0x03
#define CTL_REG_ETXSTL	 0x04
#define CTL_REG_ETXSTH	 0x05
#define CTL_REG_ETXNDL	 0x06
#define CTL_REG_ETXNDH	 0x07
#define CTL_REG_ERXSTL	 0x08
#define CTL_REG_ERXSTH	 0x09
#define CTL_REG_ERXNDL	 0x0A
#define CTL_REG_ERXNDH	 0x0B
#define CTL_REG_ERXRDPTL 0x0C
#define CTL_REG_ERXRDPTH 0x0D
#define CTL_REG_ERXWRPTL 0x0E
#define CTL_REG_ERXWRPTH 0x0F
#define CTL_REG_EDMASTL  0x10
#define CTL_REG_EDMASTH  0x11
#define CTL_REG_EDMANDL  0x12
#define CTL_REG_EDMANDH  0x13
#define CTL_REG_EDMADSTL 0x14
#define CTL_REG_EDMADSTH 0x15
#define CTL_REG_EDMACSL  0x16
#define CTL_REG_EDMACSH  0x17
/* these are common in all banks */
#define CTL_REG_EIE	 0x1B
#define CTL_REG_EIR	 0x1C
#define CTL_REG_ESTAT	 0x1D
#define CTL_REG_ECON2	 0x1E
#define CTL_REG_ECON1	 0x1F

/*
 * Control Registers in Bank 1
 */

#define CTL_REG_EHT0	0x00
#define CTL_REG_EHT1	0x01
#define CTL_REG_EHT2	0x02
#define CTL_REG_EHT3	0x03
#define CTL_REG_EHT4	0x04
#define CTL_REG_EHT5	0x05
#define CTL_REG_EHT6	0x06
#define CTL_REG_EHT7	0x07
#define CTL_REG_EPMM0	0x08
#define CTL_REG_EPMM1	0x09
#define CTL_REG_EPMM2	0x0A
#define CTL_REG_EPMM3	0x0B
#define CTL_REG_EPMM4	0x0C
#define CTL_REG_EPMM5	0x0D
#define CTL_REG_EPMM6	0x0E
#define CTL_REG_EPMM7	0x0F
#define CTL_REG_EPMCSL	0x10
#define CTL_REG_EPMCSH	0x11
#define CTL_REG_EPMOL	0x14
#define CTL_REG_EPMOH	0x15
#define CTL_REG_EWOLIE	0x16
#define CTL_REG_EWOLIR	0x17
#define CTL_REG_ERXFCON 0x18
#define CTL_REG_EPKTCNT 0x19

/*
 * Control Registers in Bank 2
 */

#define CTL_REG_MACON1	 0x00
#define CTL_REG_MACON2	 0x01
#define CTL_REG_MACON3	 0x02
#define CTL_REG_MACON4	 0x03
#define CTL_REG_MABBIPG  0x04
#define CTL_REG_MAIPGL	 0x06
#define CTL_REG_MAIPGH	 0x07
#define CTL_REG_MACLCON1 0x08
#define CTL_REG_MACLCON2 0x09
#define CTL_REG_MAMXFLL  0x0A
#define CTL_REG_MAMXFLH  0x0B
#define CTL_REG_MAPHSUP  0x0D
#define CTL_REG_MICON	 0x11
#define CTL_REG_MICMD	 0x12
#define CTL_REG_MIREGADR 0x14
#define CTL_REG_MIWRL	 0x16
#define CTL_REG_MIWRH	 0x17
#define CTL_REG_MIRDL	 0x18
#define CTL_REG_MIRDH	 0x19


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