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path: root/src/ccapi/lib/ccapi_context.c
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/*
 * $Header$
 *
 * Copyright 2006, 2007 Massachusetts Institute of Technology.
 * All Rights Reserved.
 *
 * Export of this software from the United States of America may
 * require a specific license from the United States Government.
 * It is the responsibility of any person or organization contemplating
 * export to obtain such a license before exporting.
 *
 * WITHIN THAT CONSTRAINT, permission to use, copy, modify, and
 * distribute this software and its documentation for any purpose and
 * without fee is hereby granted, provided that the above copyright
 * notice appear in all copies and that both that copyright notice and
 * this permission notice appear in supporting documentation, and that
 * the name of M.I.T. not be used in advertising or publicity pertaining
 * to distribution of the software without specific, written prior
 * permission.  Furthermore if you modify this software you must label
 * your software as modified software and not distribute it in such a
 * fashion that it might be confused with the original M.I.T. software.
 * M.I.T. makes no representations about the suitability of
 * this software for any purpose.  It is provided "as is" without express
 * or implied warranty.
 */

#include "ccapi_context.h"

#include "k5-platform.h"

#include "ccapi_ccache.h"
#include "ccapi_ccache_iterator.h"
#include "ccapi_string.h"
#include "ccapi_ipc.h"
#include "ccapi_context_change_time.h"

#include <CredentialsCache2.h>

typedef struct cci_context_d {
    cc_context_f *functions;
#if TARGET_OS_MAC
    cc_context_f *vector_functions;
#endif
    cci_identifier_t identifier;
    cc_uint32 synchronized;
    cc_time_t last_wait_for_change_time;
} *cci_context_t;

/* ------------------------------------------------------------------------ */

struct cci_context_d cci_context_initializer = { 
    NULL 
    VECTOR_FUNCTIONS_INITIALIZER,
    NULL,
    0,
    0
};

cc_context_f cci_context_f_initializer = { 
    ccapi_context_release,
    ccapi_context_get_change_time,
    ccapi_context_get_default_ccache_name,
    ccapi_context_open_ccache,
    ccapi_context_open_default_ccache,
    ccapi_context_create_ccache,
    ccapi_context_create_default_ccache,
    ccapi_context_create_new_ccache,
    ccapi_context_new_ccache_iterator,
    ccapi_context_lock,
    ccapi_context_unlock,
    ccapi_context_compare,
    ccapi_context_wait_for_change
};

static cc_int32 cci_context_sync (cci_context_t in_context, 
                                  cc_uint32     in_launch);

#ifdef TARGET_OS_MAC
#pragma mark -
#endif

MAKE_INIT_FUNCTION(cci_thread_init);

/* ------------------------------------------------------------------------ */

static int cci_thread_init (void)
{
    cc_int32 err = ccNoError;
    
    if (!err) {
        err = cci_context_change_time_thread_init ();
    }
    
    if (!err) {
        err = cci_ipc_thread_init ();
    }
    
    return err;
}

#ifdef TARGET_OS_MAC
#pragma mark -
#endif

/* ------------------------------------------------------------------------ */

cc_int32 cc_initialize (cc_context_t  *out_context,
                        cc_int32       in_version,
                        cc_int32      *out_supported_version,
                        char const   **out_vendor)
{
    cc_int32 err = ccNoError;
    cci_context_t context = NULL;
    static char *vendor_string = "MIT Kerberos CCAPI";
    
    if (!out_context) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = CALL_INIT_FUNCTION (cci_thread_init);
    }
    
    if (!err) {
        switch (in_version) { 
            case ccapi_version_2: 
            case ccapi_version_3:
            case ccapi_version_4:
            case ccapi_version_5:
            case ccapi_version_6:
            case ccapi_version_7:
                break;
            
            default: 
                err = ccErrBadAPIVersion;
                break;
        }
    }
    
    if (!err) {
        context = malloc (sizeof (*context));
        if (context) { 
            *context = cci_context_initializer;
        } else { 
            err = cci_check_error (ccErrNoMem); 
        }
    }
    
    if (!err) {
        context->functions = malloc (sizeof (*context->functions));
        if (context->functions) { 
            *context->functions = cci_context_f_initializer;
        } else { 
            err = cci_check_error (ccErrNoMem); 
        }
    }
    
    if (!err) {
        context->identifier = cci_identifier_uninitialized;

        *out_context = (cc_context_t) context;
        context = NULL; /* take ownership */
        
        if (out_supported_version) {
            *out_supported_version = ccapi_version_max;
        }
        
        if (out_vendor) {
            *out_vendor = vendor_string;
        }
    }
    
    ccapi_context_release ((cc_context_t) context);
    
    return cci_check_error (err);
}

#ifdef TARGET_OS_MAC
#pragma mark -
#endif

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_release (cc_context_t in_context)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    
    if (!in_context) { err = ccErrBadParam; }
    
    if (!err) {
        err = cci_context_sync (context, 0);
    }
    
    if (!err) {
        err =  cci_ipc_send_no_launch (cci_context_release_msg_id,
                                       context->identifier,
                                       NULL,
                                       NULL);
    }
    
    if (!err) {
        cci_identifier_release (context->identifier);
        free (context->functions);
        free (context);
    }
    
    return err;
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_get_change_time (cc_context_t  in_context,
                                        cc_time_t    *out_change_time)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t reply = NULL;
    
    if (!in_context     ) { err = cci_check_error (ccErrBadParam); }
    if (!out_change_time) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_context_sync (context, 0);
    }

    if (!err) {
        err =  cci_ipc_send_no_launch (cci_context_get_change_time_msg_id,
                                       context->identifier,
                                       NULL, &reply);
    }
    
    if (!err && cci_stream_size (reply) > 0) {
        cc_time_t change_time = 0;
        
        /* got a response from the server */
        err = cci_stream_read_time (reply, &change_time);
        
        if (!err) {
            err = cci_context_change_time_update (context->identifier,
                                                  change_time);
        }
    }
    
    if (!err) {
        err = cci_context_change_time_get (out_change_time);
    }
    
    cci_stream_release (reply);
    
    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_wait_for_change (cc_context_t  in_context)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t request = NULL;
    cci_stream_t reply = NULL;
    
    if (!in_context) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_stream_new (&request);
    }
    
    if (!err) {
        err = cci_stream_write_time (request, context->last_wait_for_change_time);
    }

    if (!err) {
        err = cci_context_sync (context, 1);
    }
    
    if (!err) {
        err = cci_ipc_send (cci_context_wait_for_change_msg_id,
			    context->identifier,
			    request, 
			    &reply);
    }

    if (!err) {
        err = cci_stream_read_time (reply, &context->last_wait_for_change_time);
    }
    
    cci_stream_release (request);
    cci_stream_release (reply);

    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_get_default_ccache_name (cc_context_t  in_context,
                                                cc_string_t  *out_name)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t reply = NULL;
    char *reply_name = NULL;
    char *name = NULL;
    
    if (!in_context) { err = cci_check_error (ccErrBadParam); }
    if (!out_name  ) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_context_sync (context, 0);
    }
    
    if (!err) {
        err =  cci_ipc_send_no_launch (cci_context_get_default_ccache_name_msg_id,
                                       context->identifier,
                                       NULL,
                                       &reply);
    }
    
    if (!err) {
        if (cci_stream_size (reply) > 0) {
            /* got a response from the server */
            err = cci_stream_read_string (reply, &reply_name);
            
            if (!err) {
                name = reply_name;
            }
        } else {
            name = k_cci_context_initial_ccache_name;
        }
    }
    
    if (!err) {
        err = cci_string_new (out_name, name);
    }
    
    cci_stream_release (reply);
    free (reply_name);
    
    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_open_ccache (cc_context_t  in_context,
                                    const char   *in_name,
                                    cc_ccache_t  *out_ccache)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t request = NULL;
    cci_stream_t reply = NULL;
    cci_identifier_t identifier = NULL;
    
    if (!in_context  ) { err = cci_check_error (ccErrBadParam); }
    if (!in_name     ) { err = cci_check_error (ccErrBadParam); }
    if (!out_ccache  ) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_stream_new (&request);
    }
    
    if (!err) {
        err = cci_stream_write_string (request, in_name);
    }
    
    if (!err) {
        err = cci_context_sync (context, 0);
    }
    
    if (!err) {
        err =  cci_ipc_send_no_launch (cci_context_open_ccache_msg_id,
                                       context->identifier,
                                       request,
                                       &reply);
    }
    
    if (!err && !(cci_stream_size (reply) > 0)) {
        err = ccErrCCacheNotFound;
    }
    
    if (!err) {
        err = cci_identifier_read (&identifier, reply);
    }
    
    if (!err) {
        err = cci_ccache_new (out_ccache, identifier);
    }
    
    cci_identifier_release (identifier);
    cci_stream_release (reply);
    cci_stream_release (request);
    
    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_open_default_ccache (cc_context_t  in_context,
                                            cc_ccache_t  *out_ccache)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t reply = NULL;
    cci_identifier_t identifier = NULL;
    
    if (!in_context) { err = cci_check_error (ccErrBadParam); }
    if (!out_ccache) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_context_sync (context, 0);
    }
    
    if (!err) {
        err =  cci_ipc_send_no_launch (cci_context_open_default_ccache_msg_id,
                                       context->identifier,
                                       NULL,
                                       &reply);
    }
    
    if (!err && !(cci_stream_size (reply) > 0)) {
        err = ccErrCCacheNotFound;
    }
    
    if (!err) {
        err = cci_identifier_read (&identifier, reply);
    }
    
    if (!err) {
        err = cci_ccache_new (out_ccache, identifier);
    }
    
    cci_identifier_release (identifier);
    cci_stream_release (reply);
    
    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_create_ccache (cc_context_t  in_context,
                                      const char   *in_name,
                                      cc_uint32     in_cred_vers,
                                      const char   *in_principal, 
                                      cc_ccache_t  *out_ccache)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t request = NULL;
    cci_stream_t reply = NULL;
    cci_identifier_t identifier = NULL;
    
    if (!in_context  ) { err = cci_check_error (ccErrBadParam); }
    if (!in_name     ) { err = cci_check_error (ccErrBadParam); }
    if (!in_principal) { err = cci_check_error (ccErrBadParam); }
    if (!out_ccache  ) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_stream_new (&request);
    }
    
    if (!err) {
        err = cci_stream_write_string (request, in_name);
    }
    
    if (!err) {
        err = cci_stream_write_uint32 (request, in_cred_vers);
    }
    
    if (!err) {
        err = cci_stream_write_string (request, in_principal);
    }
    
    if (!err) {
        err = cci_context_sync (context, 1);
    }
    
    if (!err) {
        err =  cci_ipc_send (cci_context_create_ccache_msg_id,
                             context->identifier,
                             request,
                             &reply);
    }
    
    if (!err) {
        err = cci_identifier_read (&identifier, reply);
    }
    
    if (!err) {
        err = cci_ccache_new (out_ccache, identifier);
    }
    
    cci_identifier_release (identifier);
    cci_stream_release (reply);
    cci_stream_release (request);
    
    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_create_default_ccache (cc_context_t  in_context,
                                              cc_uint32     in_cred_vers,
                                              const char   *in_principal, 
                                              cc_ccache_t  *out_ccache)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t request = NULL;
    cci_stream_t reply = NULL;
    cci_identifier_t identifier = NULL;
    
    if (!in_context  ) { err = cci_check_error (ccErrBadParam); }
    if (!in_principal) { err = cci_check_error (ccErrBadParam); }
    if (!out_ccache  ) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_stream_new (&request);
    }
    
    if (!err) {
        err = cci_stream_write_uint32 (request, in_cred_vers);
    }
    
    if (!err) {
        err = cci_stream_write_string (request, in_principal);
    }
    
    if (!err) {
        err = cci_context_sync (context, 1);
    }
    
    if (!err) {
        err =  cci_ipc_send (cci_context_create_default_ccache_msg_id,
                             context->identifier,
                             request,
                             &reply);
    }
    
    if (!err) {
        err = cci_identifier_read (&identifier, reply);
    }
    
    if (!err) {
        err = cci_ccache_new (out_ccache, identifier);
    }
    
    cci_identifier_release (identifier);
    cci_stream_release (reply);
    cci_stream_release (request);
    
    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_create_new_ccache (cc_context_t in_context,
                                          cc_uint32    in_cred_vers,
                                          const char  *in_principal, 
                                          cc_ccache_t *out_ccache)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t request = NULL;
    cci_stream_t reply = NULL;
    cci_identifier_t identifier = NULL;
    
    if (!in_context  ) { err = cci_check_error (ccErrBadParam); }
    if (!in_principal) { err = cci_check_error (ccErrBadParam); }
    if (!out_ccache  ) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_stream_new (&request);
    }
    
    if (!err) {
        err = cci_stream_write_uint32 (request, in_cred_vers);
    }
    
    if (!err) {
        err = cci_stream_write_string (request, in_principal);
    }
    
    if (!err) {
        err = cci_context_sync (context, 1);
    }
    
    if (!err) {
        err =  cci_ipc_send (cci_context_create_new_ccache_msg_id,
                             context->identifier,
                             request,
                             &reply);
    }
    
    if (!err) {
        err = cci_identifier_read (&identifier, reply);
    }
    
    if (!err) {
        err = cci_ccache_new (out_ccache, identifier);
    }
    
    cci_identifier_release (identifier);
    cci_stream_release (reply);
    cci_stream_release (request);
    
    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_new_ccache_iterator (cc_context_t          in_context,
                                            cc_ccache_iterator_t *out_iterator)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t reply = NULL;
    cci_identifier_t identifier = NULL;
    
    if (!in_context  ) { err = cci_check_error (ccErrBadParam); }
    if (!out_iterator) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_context_sync (context, 0);
    }
    
    if (!err) {
        err =  cci_ipc_send_no_launch (cci_context_new_ccache_iterator_msg_id,
                                       context->identifier,
                                       NULL,
                                       &reply);
    }
    
    if (!err) {
        if (cci_stream_size (reply) > 0) {
            err = cci_identifier_read (&identifier, reply);
        } else {
            identifier = cci_identifier_uninitialized;
        }
    }
    
    if (!err) {
        err = cci_ccache_iterator_new (out_iterator, identifier);
    }

    cci_stream_release (reply);
    cci_identifier_release (identifier);

    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_lock (cc_context_t in_context,
                             cc_uint32    in_lock_type,
                             cc_uint32    in_block)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t request = NULL;
    
    if (!in_context) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_stream_new (&request);
    }
    
    if (!err) {
        err = cci_stream_write_uint32 (request, in_lock_type);
    }
    
    if (!err) {
        err = cci_stream_write_uint32 (request, in_block);
    }
    
    if (!err) {
        err = cci_context_sync (context, 1);
    }
    
    if (!err) {
        err =  cci_ipc_send (cci_context_lock_msg_id,
                             context->identifier,
                             request,
                             NULL);
    }
    
    cci_stream_release (request);
    
    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_unlock (cc_context_t in_context)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    
    if (!in_context) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_context_sync (context, 1);
    }
    
    if (!err) {
        err =  cci_ipc_send (cci_context_unlock_msg_id,
                             context->identifier,
                             NULL,
                             NULL);
    }
    
    return cci_check_error (err);
}

/* ------------------------------------------------------------------------ */

cc_int32 ccapi_context_compare (cc_context_t  in_context,
                                cc_context_t  in_compare_to_context,
                                cc_uint32    *out_equal)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_context_t compare_to_context = (cci_context_t) in_compare_to_context;
    
    if (!in_context           ) { err = cci_check_error (ccErrBadParam); }
    if (!in_compare_to_context) { err = cci_check_error (ccErrBadParam); }
    if (!out_equal            ) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        err = cci_context_sync (context, 0);
    }
    
    if (!err) {
        err = cci_context_sync (compare_to_context, 0);
    }
    
    if (!err) {
        /* If both contexts can't talk to the server, then 
         * we assume they are equivalent */
        err = cci_identifier_compare (context->identifier, 
                                      compare_to_context->identifier,
                                      out_equal);
    }
    
    return cci_check_error (err);
}

#ifdef TARGET_OS_MAC
#pragma mark -
#endif

/* ------------------------------------------------------------------------ */

static cc_int32 cci_context_sync (cci_context_t in_context, 
                                  cc_uint32     in_launch)
{
    cc_int32 err = ccNoError;
    cci_context_t context = (cci_context_t) in_context;
    cci_stream_t reply = NULL;
    cci_identifier_t new_identifier = NULL;
    
    if (!in_context) { err = cci_check_error (ccErrBadParam); }
    
    if (!err) {
        /* Use the uninitialized identifier because we may be talking  */
        /* to a different server which would reject our identifier and */
        /* the point of this message is to sync with the server's id   */
        if (in_launch) {
            err =  cci_ipc_send (cci_context_sync_msg_id,
                                 cci_identifier_uninitialized,
                                 NULL,
                                 &reply);
        } else {
            err =  cci_ipc_send_no_launch (cci_context_sync_msg_id,
                                           cci_identifier_uninitialized,
                                           NULL,
                                           &reply);
        }
    }
    
    if (!err) {
        if (cci_stream_size (reply) > 0) {
            err = cci_identifier_read (&new_identifier, reply);
        } else {
            new_identifier = cci_identifier_uninitialized;
        }
    }
    
    if (!err) {
        cc_uint32 equal = 0;

        err = cci_identifier_compare (context->identifier, new_identifier, &equal);

        if (!err && !equal) {
            if (context->identifier) {
                cci_identifier_release (context->identifier);
            }
            context->identifier = new_identifier;
            new_identifier = NULL;  /* take ownership */
        }
    }
        
    if (!err && context->synchronized) {
        err = cci_context_change_time_sync (context->identifier);
    }
    
    if (!err && !context->synchronized) {
        /* Keep state about whether this is the first call to avoid always   */
        /* modifying the global change time on the context's first ipc call. */
        context->synchronized = 1;
    }
        
    cci_identifier_release (new_identifier);
    cci_stream_release (reply);
    
    return cci_check_error (err);
}

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// SPDX-License-Identifier: GPL-2.0+
/**************************************************************************
Intel Pro 1000 for ppcboot/das-u-boot
Drivers are port from Intel's Linux driver e1000-4.3.15
and from Etherboot pro 1000 driver by mrakes at vivato dot net
tested on both gig copper and gig fiber boards
***************************************************************************/
/*******************************************************************************


  Copyright(c) 1999 - 2002 Intel Corporation. All rights reserved.


  Contact Information:
  Linux NICS <linux.nics@intel.com>
  Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497

*******************************************************************************/
/*
 *  Copyright (C) Archway Digital Solutions.
 *
 *  written by Chrsitopher Li <cli at arcyway dot com> or <chrisl at gnuchina dot org>
 *  2/9/2002
 *
 *  Copyright (C) Linux Networx.
 *  Massive upgrade to work with the new intel gigabit NICs.
 *  <ebiederman at lnxi dot com>
 *
 *  Copyright 2011 Freescale Semiconductor, Inc.
 */

#include <common.h>
#include <command.h>
#include <cpu_func.h>
#include <dm.h>
#include <errno.h>
#include <log.h>
#include <malloc.h>
#include <memalign.h>
#include <net.h>
#include <pci.h>
#include <linux/delay.h>
#include "e1000.h"
#include <asm/cache.h>

#define TOUT_LOOP   100000

#ifdef CONFIG_DM_ETH
#define virt_to_bus(devno, v)	dm_pci_virt_to_mem(devno, (void *) (v))
#define bus_to_phys(devno, a)	dm_pci_mem_to_phys(devno, a)
#else
#define virt_to_bus(devno, v)	pci_virt_to_mem(devno, (void *) (v))
#define bus_to_phys(devno, a)	pci_mem_to_phys(devno, a)
#endif

#define E1000_DEFAULT_PCI_PBA	0x00000030
#define E1000_DEFAULT_PCIE_PBA	0x000a0026

/* NIC specific static variables go here */

/* Intel i210 needs the DMA descriptor rings aligned to 128b */
#define E1000_BUFFER_ALIGN	128

/*
 * TODO(sjg@chromium.org): Even with driver model we share these buffers.
 * Concurrent receiving on multiple active Ethernet devices will not work.
 * Normally U-Boot does not support this anyway. To fix it in this driver,
 * move these buffers and the tx/rx pointers to struct e1000_hw.
 */
DEFINE_ALIGN_BUFFER(struct e1000_tx_desc, tx_base, 16, E1000_BUFFER_ALIGN);
DEFINE_ALIGN_BUFFER(struct e1000_rx_desc, rx_base, 16, E1000_BUFFER_ALIGN);
DEFINE_ALIGN_BUFFER(unsigned char, packet, 4096, E1000_BUFFER_ALIGN);

static int tx_tail;
static int rx_tail, rx_last;
#ifdef CONFIG_DM_ETH
static int num_cards;	/* Number of E1000 devices seen so far */
#endif

static struct pci_device_id e1000_supported[] = {
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82542) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_FIBER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82543GC_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544EI_FIBER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82544GC_LOM) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545GM_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541GI_LF) },
	/* E1000 PCIe card */
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_FIBER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571PT_QUAD_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_FIBER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_QUAD_COPPER_LOWPROFILE) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_DUAL) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82571EB_SERDES_QUAD) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_FIBER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI_SERDES) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82572EI) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573E_IAMT) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82573L) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82574L) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546GB_QUAD_COPPER_KSP3) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_DPT) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_DPT) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_COPPER_SPT) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_80003ES2LAN_SERDES_SPT) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I211_COPPER) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS) },
	{ PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I210_1000BASEKX) },

	{}
};

/* Function forward declarations */
static int e1000_setup_link(struct e1000_hw *hw);
static int e1000_setup_fiber_link(struct e1000_hw *hw);
static int e1000_setup_copper_link(struct e1000_hw *hw);
static int e1000_phy_setup_autoneg(struct e1000_hw *hw);
static void e1000_config_collision_dist(struct e1000_hw *hw);
static int e1000_config_mac_to_phy(struct e1000_hw *hw);
static int e1000_config_fc_after_link_up(struct e1000_hw *hw);
static int e1000_check_for_link(struct e1000_hw *hw);
static int e1000_wait_autoneg(struct e1000_hw *hw);
static int e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed,
				       uint16_t * duplex);
static int e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
			      uint16_t * phy_data);
static int e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr,
			       uint16_t phy_data);
static int32_t e1000_phy_hw_reset(struct e1000_hw *hw);
static int e1000_phy_reset(struct e1000_hw *hw);
static int e1000_detect_gig_phy(struct e1000_hw *hw);
static void e1000_set_media_type(struct e1000_hw *hw);

static int32_t e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask);
static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask);
static int32_t e1000_check_phy_reset_block(struct e1000_hw *hw);

#ifndef CONFIG_E1000_NO_NVM
static void e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw);
static int32_t e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw);
static int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
		uint16_t words,
		uint16_t *data);
/******************************************************************************
 * Raises the EEPROM's clock input.
 *
 * hw - Struct containing variables accessed by shared code
 * eecd - EECD's current value
 *****************************************************************************/
void e1000_raise_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
{
	/* Raise the clock input to the EEPROM (by setting the SK bit), and then
	 * wait 50 microseconds.
	 */
	*eecd = *eecd | E1000_EECD_SK;
	E1000_WRITE_REG(hw, EECD, *eecd);
	E1000_WRITE_FLUSH(hw);
	udelay(50);
}

/******************************************************************************
 * Lowers the EEPROM's clock input.
 *
 * hw - Struct containing variables accessed by shared code
 * eecd - EECD's current value
 *****************************************************************************/
void e1000_lower_ee_clk(struct e1000_hw *hw, uint32_t * eecd)
{
	/* Lower the clock input to the EEPROM (by clearing the SK bit), and then
	 * wait 50 microseconds.
	 */
	*eecd = *eecd & ~E1000_EECD_SK;
	E1000_WRITE_REG(hw, EECD, *eecd);
	E1000_WRITE_FLUSH(hw);
	udelay(50);
}

/******************************************************************************
 * Shift data bits out to the EEPROM.
 *
 * hw - Struct containing variables accessed by shared code
 * data - data to send to the EEPROM
 * count - number of bits to shift out
 *****************************************************************************/
static void
e1000_shift_out_ee_bits(struct e1000_hw *hw, uint16_t data, uint16_t count)
{
	uint32_t eecd;
	uint32_t mask;

	/* We need to shift "count" bits out to the EEPROM. So, value in the
	 * "data" parameter will be shifted out to the EEPROM one bit at a time.
	 * In order to do this, "data" must be broken down into bits.
	 */
	mask = 0x01 << (count - 1);
	eecd = E1000_READ_REG(hw, EECD);
	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
	do {
		/* A "1" is shifted out to the EEPROM by setting bit "DI" to a "1",
		 * and then raising and then lowering the clock (the SK bit controls
		 * the clock input to the EEPROM).  A "0" is shifted out to the EEPROM
		 * by setting "DI" to "0" and then raising and then lowering the clock.
		 */
		eecd &= ~E1000_EECD_DI;

		if (data & mask)
			eecd |= E1000_EECD_DI;

		E1000_WRITE_REG(hw, EECD, eecd);
		E1000_WRITE_FLUSH(hw);

		udelay(50);

		e1000_raise_ee_clk(hw, &eecd);
		e1000_lower_ee_clk(hw, &eecd);

		mask = mask >> 1;

	} while (mask);

	/* We leave the "DI" bit set to "0" when we leave this routine. */
	eecd &= ~E1000_EECD_DI;
	E1000_WRITE_REG(hw, EECD, eecd);
}

/******************************************************************************
 * Shift data bits in from the EEPROM
 *
 * hw - Struct containing variables accessed by shared code
 *****************************************************************************/
static uint16_t
e1000_shift_in_ee_bits(struct e1000_hw *hw, uint16_t count)
{
	uint32_t eecd;
	uint32_t i;
	uint16_t data;

	/* In order to read a register from the EEPROM, we need to shift 'count'
	 * bits in from the EEPROM. Bits are "shifted in" by raising the clock
	 * input to the EEPROM (setting the SK bit), and then reading the
	 * value of the "DO" bit.  During this "shifting in" process the
	 * "DI" bit should always be clear.
	 */

	eecd = E1000_READ_REG(hw, EECD);

	eecd &= ~(E1000_EECD_DO | E1000_EECD_DI);
	data = 0;

	for (i = 0; i < count; i++) {
		data = data << 1;
		e1000_raise_ee_clk(hw, &eecd);

		eecd = E1000_READ_REG(hw, EECD);

		eecd &= ~(E1000_EECD_DI);
		if (eecd & E1000_EECD_DO)
			data |= 1;

		e1000_lower_ee_clk(hw, &eecd);
	}

	return data;
}

/******************************************************************************
 * Returns EEPROM to a "standby" state
 *
 * hw - Struct containing variables accessed by shared code
 *****************************************************************************/
void e1000_standby_eeprom(struct e1000_hw *hw)
{
	struct e1000_eeprom_info *eeprom = &hw->eeprom;
	uint32_t eecd;

	eecd = E1000_READ_REG(hw, EECD);

	if (eeprom->type == e1000_eeprom_microwire) {
		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
		E1000_WRITE_REG(hw, EECD, eecd);
		E1000_WRITE_FLUSH(hw);
		udelay(eeprom->delay_usec);

		/* Clock high */
		eecd |= E1000_EECD_SK;
		E1000_WRITE_REG(hw, EECD, eecd);
		E1000_WRITE_FLUSH(hw);
		udelay(eeprom->delay_usec);

		/* Select EEPROM */
		eecd |= E1000_EECD_CS;
		E1000_WRITE_REG(hw, EECD, eecd);
		E1000_WRITE_FLUSH(hw);
		udelay(eeprom->delay_usec);

		/* Clock low */
		eecd &= ~E1000_EECD_SK;
		E1000_WRITE_REG(hw, EECD, eecd);
		E1000_WRITE_FLUSH(hw);
		udelay(eeprom->delay_usec);
	} else if (eeprom->type == e1000_eeprom_spi) {
		/* Toggle CS to flush commands */
		eecd |= E1000_EECD_CS;
		E1000_WRITE_REG(hw, EECD, eecd);
		E1000_WRITE_FLUSH(hw);
		udelay(eeprom->delay_usec);
		eecd &= ~E1000_EECD_CS;
		E1000_WRITE_REG(hw, EECD, eecd);
		E1000_WRITE_FLUSH(hw);
		udelay(eeprom->delay_usec);
	}
}

/***************************************************************************
* Description:     Determines if the onboard NVM is FLASH or EEPROM.
*
* hw - Struct containing variables accessed by shared code
****************************************************************************/
static bool e1000_is_onboard_nvm_eeprom(struct e1000_hw *hw)
{
	uint32_t eecd = 0;

	DEBUGFUNC();

	if (hw->mac_type == e1000_ich8lan)
		return false;

	if (hw->mac_type == e1000_82573 || hw->mac_type == e1000_82574) {
		eecd = E1000_READ_REG(hw, EECD);

		/* Isolate bits 15 & 16 */
		eecd = ((eecd >> 15) & 0x03);

		/* If both bits are set, device is Flash type */
		if (eecd == 0x03)
			return false;
	}
	return true;
}

/******************************************************************************
 * Prepares EEPROM for access
 *
 * hw - Struct containing variables accessed by shared code
 *
 * Lowers EEPROM clock. Clears input pin. Sets the chip select pin. This
 * function should be called before issuing a command to the EEPROM.
 *****************************************************************************/
int32_t e1000_acquire_eeprom(struct e1000_hw *hw)
{
	struct e1000_eeprom_info *eeprom = &hw->eeprom;
	uint32_t eecd, i = 0;

	DEBUGFUNC();

	if (e1000_swfw_sync_acquire(hw, E1000_SWFW_EEP_SM))
		return -E1000_ERR_SWFW_SYNC;
	eecd = E1000_READ_REG(hw, EECD);

	if (hw->mac_type != e1000_82573 && hw->mac_type != e1000_82574) {
		/* Request EEPROM Access */
		if (hw->mac_type > e1000_82544) {
			eecd |= E1000_EECD_REQ;
			E1000_WRITE_REG(hw, EECD, eecd);
			eecd = E1000_READ_REG(hw, EECD);
			while ((!(eecd & E1000_EECD_GNT)) &&
				(i < E1000_EEPROM_GRANT_ATTEMPTS)) {
				i++;
				udelay(5);
				eecd = E1000_READ_REG(hw, EECD);
			}
			if (!(eecd & E1000_EECD_GNT)) {
				eecd &= ~E1000_EECD_REQ;
				E1000_WRITE_REG(hw, EECD, eecd);
				DEBUGOUT("Could not acquire EEPROM grant\n");
				return -E1000_ERR_EEPROM;
			}
		}
	}

	/* Setup EEPROM for Read/Write */

	if (eeprom->type == e1000_eeprom_microwire) {
		/* Clear SK and DI */
		eecd &= ~(E1000_EECD_DI | E1000_EECD_SK);
		E1000_WRITE_REG(hw, EECD, eecd);

		/* Set CS */
		eecd |= E1000_EECD_CS;
		E1000_WRITE_REG(hw, EECD, eecd);
	} else if (eeprom->type == e1000_eeprom_spi) {
		/* Clear SK and CS */
		eecd &= ~(E1000_EECD_CS | E1000_EECD_SK);
		E1000_WRITE_REG(hw, EECD, eecd);
		udelay(1);
	}

	return E1000_SUCCESS;
}

/******************************************************************************
 * Sets up eeprom variables in the hw struct.  Must be called after mac_type
 * is configured.  Additionally, if this is ICH8, the flash controller GbE
 * registers must be mapped, or this will crash.
 *
 * hw - Struct containing variables accessed by shared code
 *****************************************************************************/
static int32_t e1000_init_eeprom_params(struct e1000_hw *hw)
{
	struct e1000_eeprom_info *eeprom = &hw->eeprom;
	uint32_t eecd;
	int32_t ret_val = E1000_SUCCESS;
	uint16_t eeprom_size;

	if (hw->mac_type == e1000_igb)
		eecd = E1000_READ_REG(hw, I210_EECD);
	else
		eecd = E1000_READ_REG(hw, EECD);

	DEBUGFUNC();

	switch (hw->mac_type) {
	case e1000_82542_rev2_0:
	case e1000_82542_rev2_1:
	case e1000_82543:
	case e1000_82544:
		eeprom->type = e1000_eeprom_microwire;
		eeprom->word_size = 64;
		eeprom->opcode_bits = 3;
		eeprom->address_bits = 6;
		eeprom->delay_usec = 50;
		eeprom->use_eerd = false;
		eeprom->use_eewr = false;
	break;
	case e1000_82540:
	case e1000_82545:
	case e1000_82545_rev_3:
	case e1000_82546:
	case e1000_82546_rev_3:
		eeprom->type = e1000_eeprom_microwire;
		eeprom->opcode_bits = 3;
		eeprom->delay_usec = 50;
		if (eecd & E1000_EECD_SIZE) {
			eeprom->word_size = 256;
			eeprom->address_bits = 8;
		} else {
			eeprom->word_size = 64;
			eeprom->address_bits = 6;
		}
		eeprom->use_eerd = false;
		eeprom->use_eewr = false;
		break;
	case e1000_82541:
	case e1000_82541_rev_2:
	case e1000_82547:
	case e1000_82547_rev_2:
		if (eecd & E1000_EECD_TYPE) {
			eeprom->type = e1000_eeprom_spi;
			eeprom->opcode_bits = 8;
			eeprom->delay_usec = 1;
			if (eecd & E1000_EECD_ADDR_BITS) {
				eeprom->page_size = 32;
				eeprom->address_bits = 16;
			} else {
				eeprom->page_size = 8;
				eeprom->address_bits = 8;
			}
		} else {
			eeprom->type = e1000_eeprom_microwire;
			eeprom->opcode_bits = 3;
			eeprom->delay_usec = 50;
			if (eecd & E1000_EECD_ADDR_BITS) {
				eeprom->word_size = 256;
				eeprom->address_bits = 8;
			} else {
				eeprom->word_size = 64;
				eeprom->address_bits = 6;
			}
		}
		eeprom->use_eerd = false;
		eeprom->use_eewr = false;
		break;
	case e1000_82571:
	case e1000_82572:
		eeprom->type = e1000_eeprom_spi;
		eeprom->opcode_bits = 8;
		eeprom->delay_usec = 1;
		if (eecd & E1000_EECD_ADDR_BITS) {
			eeprom->page_size = 32;
			eeprom->address_bits = 16;
		} else {
			eeprom->page_size = 8;
			eeprom->address_bits = 8;
		}
		eeprom->use_eerd = false;
		eeprom->use_eewr = false;
		break;
	case e1000_82573:
	case e1000_82574:
		eeprom->type = e1000_eeprom_spi;
		eeprom->opcode_bits = 8;
		eeprom->delay_usec = 1;
		if (eecd & E1000_EECD_ADDR_BITS) {
			eeprom->page_size = 32;
			eeprom->address_bits = 16;
		} else {
			eeprom->page_size = 8;
			eeprom->address_bits = 8;
		}
		if (e1000_is_onboard_nvm_eeprom(hw) == false) {
			eeprom->use_eerd = true;
			eeprom->use_eewr = true;

			eeprom->type = e1000_eeprom_flash;
			eeprom->word_size = 2048;

		/* Ensure that the Autonomous FLASH update bit is cleared due to
		 * Flash update issue on parts which use a FLASH for NVM. */
			eecd &= ~E1000_EECD_AUPDEN;
			E1000_WRITE_REG(hw, EECD, eecd);
		}
		break;
	case e1000_80003es2lan:
		eeprom->type = e1000_eeprom_spi;
		eeprom->opcode_bits = 8;
		eeprom->delay_usec = 1;
		if (eecd & E1000_EECD_ADDR_BITS) {
			eeprom->page_size = 32;
			eeprom->address_bits = 16;
		} else {
			eeprom->page_size = 8;
			eeprom->address_bits = 8;
		}
		eeprom->use_eerd = true;
		eeprom->use_eewr = false;
		break;
	case e1000_igb:
		/* i210 has 4k of iNVM mapped as EEPROM */
		eeprom->type = e1000_eeprom_invm;
		eeprom->opcode_bits = 8;
		eeprom->delay_usec = 1;
		eeprom->page_size = 32;
		eeprom->address_bits = 16;
		eeprom->use_eerd = true;
		eeprom->use_eewr = false;
		break;
	default:
		break;
	}

	if (eeprom->type == e1000_eeprom_spi ||
	    eeprom->type == e1000_eeprom_invm) {
		/* eeprom_size will be an enum [0..8] that maps
		 * to eeprom sizes 128B to
		 * 32KB (incremented by powers of 2).
		 */
		if (hw->mac_type <= e1000_82547_rev_2) {
			/* Set to default value for initial eeprom read. */
			eeprom->word_size = 64;
			ret_val = e1000_read_eeprom(hw, EEPROM_CFG, 1,
					&eeprom_size);
			if (ret_val)
				return ret_val;
			eeprom_size = (eeprom_size & EEPROM_SIZE_MASK)
				>> EEPROM_SIZE_SHIFT;
			/* 256B eeprom size was not supported in earlier
			 * hardware, so we bump eeprom_size up one to
			 * ensure that "1" (which maps to 256B) is never
			 * the result used in the shifting logic below. */
			if (eeprom_size)
				eeprom_size++;
		} else {
			eeprom_size = (uint16_t)((eecd &
				E1000_EECD_SIZE_EX_MASK) >>
				E1000_EECD_SIZE_EX_SHIFT);
		}

		eeprom->word_size = 1 << (eeprom_size + EEPROM_WORD_SIZE_SHIFT);
	}
	return ret_val;
}

/******************************************************************************
 * Polls the status bit (bit 1) of the EERD to determine when the read is done.
 *
 * hw - Struct containing variables accessed by shared code
 *****************************************************************************/
static int32_t
e1000_poll_eerd_eewr_done(struct e1000_hw *hw, int eerd)
{
	uint32_t attempts = 100000;
	uint32_t i, reg = 0;
	int32_t done = E1000_ERR_EEPROM;

	for (i = 0; i < attempts; i++) {
		if (eerd == E1000_EEPROM_POLL_READ) {
			if (hw->mac_type == e1000_igb)
				reg = E1000_READ_REG(hw, I210_EERD);
			else
				reg = E1000_READ_REG(hw, EERD);
		} else {
			if (hw->mac_type == e1000_igb)
				reg = E1000_READ_REG(hw, I210_EEWR);
			else
				reg = E1000_READ_REG(hw, EEWR);
		}

		if (reg & E1000_EEPROM_RW_REG_DONE) {
			done = E1000_SUCCESS;
			break;
		}
		udelay(5);
	}

	return done;
}

/******************************************************************************
 * Reads a 16 bit word from the EEPROM using the EERD register.
 *
 * hw - Struct containing variables accessed by shared code
 * offset - offset of  word in the EEPROM to read
 * data - word read from the EEPROM
 * words - number of words to read
 *****************************************************************************/
static int32_t
e1000_read_eeprom_eerd(struct e1000_hw *hw,
			uint16_t offset,
			uint16_t words,
			uint16_t *data)
{
	uint32_t i, eerd = 0;
	int32_t error = 0;

	for (i = 0; i < words; i++) {
		eerd = ((offset+i) << E1000_EEPROM_RW_ADDR_SHIFT) +
			E1000_EEPROM_RW_REG_START;

		if (hw->mac_type == e1000_igb)
			E1000_WRITE_REG(hw, I210_EERD, eerd);
		else
			E1000_WRITE_REG(hw, EERD, eerd);

		error = e1000_poll_eerd_eewr_done(hw, E1000_EEPROM_POLL_READ);

		if (error)
			break;

		if (hw->mac_type == e1000_igb) {
			data[i] = (E1000_READ_REG(hw, I210_EERD) >>
				E1000_EEPROM_RW_REG_DATA);
		} else {
			data[i] = (E1000_READ_REG(hw, EERD) >>
				E1000_EEPROM_RW_REG_DATA);
		}

	}

	return error;
}

void e1000_release_eeprom(struct e1000_hw *hw)
{
	uint32_t eecd;

	DEBUGFUNC();

	eecd = E1000_READ_REG(hw, EECD);

	if (hw->eeprom.type == e1000_eeprom_spi) {
		eecd |= E1000_EECD_CS;  /* Pull CS high */
		eecd &= ~E1000_EECD_SK; /* Lower SCK */

		E1000_WRITE_REG(hw, EECD, eecd);

		udelay(hw->eeprom.delay_usec);
	} else if (hw->eeprom.type == e1000_eeprom_microwire) {
		/* cleanup eeprom */

		/* CS on Microwire is active-high */
		eecd &= ~(E1000_EECD_CS | E1000_EECD_DI);

		E1000_WRITE_REG(hw, EECD, eecd);

		/* Rising edge of clock */
		eecd |= E1000_EECD_SK;
		E1000_WRITE_REG(hw, EECD, eecd);
		E1000_WRITE_FLUSH(hw);
		udelay(hw->eeprom.delay_usec);

		/* Falling edge of clock */
		eecd &= ~E1000_EECD_SK;
		E1000_WRITE_REG(hw, EECD, eecd);
		E1000_WRITE_FLUSH(hw);
		udelay(hw->eeprom.delay_usec);
	}

	/* Stop requesting EEPROM access */
	if (hw->mac_type > e1000_82544) {
		eecd &= ~E1000_EECD_REQ;
		E1000_WRITE_REG(hw, EECD, eecd);
	}

	e1000_swfw_sync_release(hw, E1000_SWFW_EEP_SM);
}

/******************************************************************************
 * Reads a 16 bit word from the EEPROM.
 *
 * hw - Struct containing variables accessed by shared code
 *****************************************************************************/
static int32_t
e1000_spi_eeprom_ready(struct e1000_hw *hw)
{
	uint16_t retry_count = 0;
	uint8_t spi_stat_reg;

	DEBUGFUNC();

	/* Read "Status Register" repeatedly until the LSB is cleared.  The
	 * EEPROM will signal that the command has been completed by clearing
	 * bit 0 of the internal status register.  If it's not cleared within
	 * 5 milliseconds, then error out.
	 */
	retry_count = 0;
	do {
		e1000_shift_out_ee_bits(hw, EEPROM_RDSR_OPCODE_SPI,
			hw->eeprom.opcode_bits);
		spi_stat_reg = (uint8_t)e1000_shift_in_ee_bits(hw, 8);
		if (!(spi_stat_reg & EEPROM_STATUS_RDY_SPI))
			break;

		udelay(5);
		retry_count += 5;

		e1000_standby_eeprom(hw);
	} while (retry_count < EEPROM_MAX_RETRY_SPI);

	/* ATMEL SPI write time could vary from 0-20mSec on 3.3V devices (and
	 * only 0-5mSec on 5V devices)
	 */
	if (retry_count >= EEPROM_MAX_RETRY_SPI) {
		DEBUGOUT("SPI EEPROM Status error\n");
		return -E1000_ERR_EEPROM;
	}

	return E1000_SUCCESS;
}

/******************************************************************************
 * Reads a 16 bit word from the EEPROM.
 *
 * hw - Struct containing variables accessed by shared code
 * offset - offset of  word in the EEPROM to read
 * data - word read from the EEPROM
 *****************************************************************************/
static int32_t
e1000_read_eeprom(struct e1000_hw *hw, uint16_t offset,
		uint16_t words, uint16_t *data)
{
	struct e1000_eeprom_info *eeprom = &hw->eeprom;
	uint32_t i = 0;

	DEBUGFUNC();

	/* If eeprom is not yet detected, do so now */
	if (eeprom->word_size == 0)
		e1000_init_eeprom_params(hw);

	/* A check for invalid values:  offset too large, too many words,
	 * and not enough words.
	 */
	if ((offset >= eeprom->word_size) ||
		(words > eeprom->word_size - offset) ||
		(words == 0)) {
		DEBUGOUT("\"words\" parameter out of bounds."
			"Words = %d, size = %d\n", offset, eeprom->word_size);
		return -E1000_ERR_EEPROM;
	}

	/* EEPROM's that don't use EERD to read require us to bit-bang the SPI
	 * directly. In this case, we need to acquire the EEPROM so that
	 * FW or other port software does not interrupt.
	 */
	if (e1000_is_onboard_nvm_eeprom(hw) == true &&
		hw->eeprom.use_eerd == false) {

		/* Prepare the EEPROM for bit-bang reading */
		if (e1000_acquire_eeprom(hw) != E1000_SUCCESS)
			return -E1000_ERR_EEPROM;
	}

	/* Eerd register EEPROM access requires no eeprom aquire/release */
	if (eeprom->use_eerd == true)
		return e1000_read_eeprom_eerd(hw, offset, words, data);

	/* Set up the SPI or Microwire EEPROM for bit-bang reading.  We have
	 * acquired the EEPROM at this point, so any returns should relase it */
	if (eeprom->type == e1000_eeprom_spi) {
		uint16_t word_in;
		uint8_t read_opcode = EEPROM_READ_OPCODE_SPI;

		if (e1000_spi_eeprom_ready(hw)) {
			e1000_release_eeprom(hw);
			return -E1000_ERR_EEPROM;
		}

		e1000_standby_eeprom(hw);

		/* Some SPI eeproms use the 8th address bit embedded in
		 * the opcode */
		if ((eeprom->address_bits == 8) && (offset >= 128))
			read_opcode |= EEPROM_A8_OPCODE_SPI;

		/* Send the READ command (opcode + addr)  */
		e1000_shift_out_ee_bits(hw, read_opcode, eeprom->opcode_bits);
		e1000_shift_out_ee_bits(hw, (uint16_t)(offset*2),
				eeprom->address_bits);

		/* Read the data.  The address of the eeprom internally
		 * increments with each byte (spi) being read, saving on the
		 * overhead of eeprom setup and tear-down.  The address
		 * counter will roll over if reading beyond the size of
		 * the eeprom, thus allowing the entire memory to be read
		 * starting from any offset. */
		for (i = 0; i < words; i++) {
			word_in = e1000_shift_in_ee_bits(hw, 16);
			data[i] = (word_in >> 8) | (word_in << 8);
		}
	} else if (eeprom->type == e1000_eeprom_microwire) {
		for (i = 0; i < words; i++) {
			/* Send the READ command (opcode + addr)  */
			e1000_shift_out_ee_bits(hw,
				EEPROM_READ_OPCODE_MICROWIRE,
				eeprom->opcode_bits);
			e1000_shift_out_ee_bits(hw, (uint16_t)(offset + i),
				eeprom->address_bits);

			/* Read the data.  For microwire, each word requires
			 * the overhead of eeprom setup and tear-down. */
			data[i] = e1000_shift_in_ee_bits(hw, 16);
			e1000_standby_eeprom(hw);
		}
	}

	/* End this read operation */
	e1000_release_eeprom(hw);

	return E1000_SUCCESS;
}

#ifndef CONFIG_DM_ETH
/******************************************************************************
 *  e1000_write_eeprom_srwr - Write to Shadow Ram using EEWR
 *  @hw: pointer to the HW structure
 *  @offset: offset within the Shadow Ram to be written to
 *  @words: number of words to write
 *  @data: 16 bit word(s) to be written to the Shadow Ram
 *
 *  Writes data to Shadow Ram at offset using EEWR register.
 *
 *  If e1000_update_eeprom_checksum_i210 is not called after this function, the
 *  Shadow Ram will most likely contain an invalid checksum.
 *****************************************************************************/
static int32_t e1000_write_eeprom_srwr(struct e1000_hw *hw, uint16_t offset,
				       uint16_t words, uint16_t *data)
{
	struct e1000_eeprom_info *eeprom = &hw->eeprom;
	uint32_t i, k, eewr = 0;
	uint32_t attempts = 100000;
	int32_t ret_val = 0;

	/* A check for invalid values:  offset too large, too many words,
	 * too many words for the offset, and not enough words.
	 */
	if ((offset >= eeprom->word_size) ||
	    (words > (eeprom->word_size - offset)) || (words == 0)) {
		DEBUGOUT("nvm parameter(s) out of bounds\n");
		ret_val = -E1000_ERR_EEPROM;
		goto out;
	}

	for (i = 0; i < words; i++) {
		eewr = ((offset + i) << E1000_EEPROM_RW_ADDR_SHIFT)
				| (data[i] << E1000_EEPROM_RW_REG_DATA) |
				E1000_EEPROM_RW_REG_START;

		E1000_WRITE_REG(hw, I210_EEWR, eewr);

		for (k = 0; k < attempts; k++) {
			if (E1000_EEPROM_RW_REG_DONE &
			    E1000_READ_REG(hw, I210_EEWR)) {
				ret_val = 0;
				break;
			}
			udelay(5);
		}

		if (ret_val) {
			DEBUGOUT("Shadow RAM write EEWR timed out\n");
			break;
		}
	}

out:
	return ret_val;
}

/******************************************************************************
 *  e1000_pool_flash_update_done_i210 - Pool FLUDONE status.
 *  @hw: pointer to the HW structure
 *
 *****************************************************************************/
static int32_t e1000_pool_flash_update_done_i210(struct e1000_hw *hw)
{
	int32_t ret_val = -E1000_ERR_EEPROM;
	uint32_t i, reg;

	for (i = 0; i < E1000_FLUDONE_ATTEMPTS; i++) {
		reg = E1000_READ_REG(hw, EECD);
		if (reg & E1000_EECD_FLUDONE_I210) {
			ret_val = 0;
			break;
		}
		udelay(5);
	}

	return ret_val;
}

/******************************************************************************
 *  e1000_update_flash_i210 - Commit EEPROM to the flash
 *  @hw: pointer to the HW structure
 *
 *****************************************************************************/
static int32_t e1000_update_flash_i210(struct e1000_hw *hw)
{
	int32_t ret_val = 0;
	uint32_t flup;

	ret_val = e1000_pool_flash_update_done_i210(hw);
	if (ret_val == -E1000_ERR_EEPROM) {
		DEBUGOUT("Flash update time out\n");
		goto out;
	}

	flup = E1000_READ_REG(hw, EECD) | E1000_EECD_FLUPD_I210;
	E1000_WRITE_REG(hw, EECD, flup);

	ret_val = e1000_pool_flash_update_done_i210(hw);
	if (ret_val)
		DEBUGOUT("Flash update time out\n");
	else
		DEBUGOUT("Flash update complete\n");

out:
	return ret_val;
}

/******************************************************************************
 *  e1000_update_eeprom_checksum_i210 - Update EEPROM checksum
 *  @hw: pointer to the HW structure
 *
 *  Updates the EEPROM checksum by reading/adding each word of the EEPROM
 *  up to the checksum.  Then calculates the EEPROM checksum and writes the
 *  value to the EEPROM. Next commit EEPROM data onto the Flash.
 *****************************************************************************/
static int32_t e1000_update_eeprom_checksum_i210(struct e1000_hw *hw)
{
	int32_t ret_val = 0;
	uint16_t checksum = 0;
	uint16_t i, nvm_data;

	/* Read the first word from the EEPROM. If this times out or fails, do
	 * not continue or we could be in for a very long wait while every
	 * EEPROM read fails
	 */
	ret_val = e1000_read_eeprom_eerd(hw, 0, 1, &nvm_data);
	if (ret_val) {
		DEBUGOUT("EEPROM read failed\n");
		goto out;
	}

	if (!(e1000_get_hw_eeprom_semaphore(hw))) {
		/* Do not use hw->nvm.ops.write, hw->nvm.ops.read
		 * because we do not want to take the synchronization
		 * semaphores twice here.
		 */

		for (i = 0; i < EEPROM_CHECKSUM_REG; i++) {
			ret_val = e1000_read_eeprom_eerd(hw, i, 1, &nvm_data);
			if (ret_val) {
				e1000_put_hw_eeprom_semaphore(hw);
				DEBUGOUT("EEPROM Read Error while updating checksum.\n");
				goto out;
			}
			checksum += nvm_data;
		}
		checksum = (uint16_t)EEPROM_SUM - checksum;
		ret_val = e1000_write_eeprom_srwr(hw, EEPROM_CHECKSUM_REG, 1,
						  &checksum);
		if (ret_val) {
			e1000_put_hw_eeprom_semaphore(hw);
			DEBUGOUT("EEPROM Write Error while updating checksum.\n");
			goto out;
		}

		e1000_put_hw_eeprom_semaphore(hw);

		ret_val = e1000_update_flash_i210(hw);
	} else {
		ret_val = -E1000_ERR_SWFW_SYNC;
	}

out:
	return ret_val;
}
#endif

/******************************************************************************
 * Verifies that the EEPROM has a valid checksum
 *
 * hw - Struct containing variables accessed by shared code
 *
 * Reads the first 64 16 bit words of the EEPROM and sums the values read.
 * If the the sum of the 64 16 bit words is 0xBABA, the EEPROM's checksum is
 * valid.
 *****************************************************************************/
static int e1000_validate_eeprom_checksum(struct e1000_hw *hw)
{
	uint16_t i, checksum, checksum_reg, *buf;

	DEBUGFUNC();

	/* Allocate a temporary buffer */
	buf = malloc(sizeof(buf[0]) * (EEPROM_CHECKSUM_REG + 1));
	if (!buf) {
		E1000_ERR(hw, "Unable to allocate EEPROM buffer!\n");
		return -E1000_ERR_EEPROM;
	}

	/* Read the EEPROM */
	if (e1000_read_eeprom(hw, 0, EEPROM_CHECKSUM_REG + 1, buf) < 0) {
		E1000_ERR(hw, "Unable to read EEPROM!\n");
		return -E1000_ERR_EEPROM;
	}

	/* Compute the checksum */
	checksum = 0;
	for (i = 0; i < EEPROM_CHECKSUM_REG; i++)
		checksum += buf[i];
	checksum = ((uint16_t)EEPROM_SUM) - checksum;
	checksum_reg = buf[i];

	/* Verify it! */
	if (checksum == checksum_reg)
		return 0;

	/* Hrm, verification failed, print an error */
	E1000_ERR(hw, "EEPROM checksum is incorrect!\n");
	E1000_ERR(hw, "  ...register was 0x%04hx, calculated 0x%04hx\n",
		  checksum_reg, checksum);

	return -E1000_ERR_EEPROM;
}
#endif /* CONFIG_E1000_NO_NVM */

/*****************************************************************************
 * Set PHY to class A mode
 * Assumes the following operations will follow to enable the new class mode.
 *  1. Do a PHY soft reset
 *  2. Restart auto-negotiation or force link.
 *
 * hw - Struct containing variables accessed by shared code
 ****************************************************************************/
static int32_t
e1000_set_phy_mode(struct e1000_hw *hw)
{
#ifndef CONFIG_E1000_NO_NVM
	int32_t ret_val;
	uint16_t eeprom_data;

	DEBUGFUNC();

	if ((hw->mac_type == e1000_82545_rev_3) &&
		(hw->media_type == e1000_media_type_copper)) {
		ret_val = e1000_read_eeprom(hw, EEPROM_PHY_CLASS_WORD,
				1, &eeprom_data);
		if (ret_val)
			return ret_val;

		if ((eeprom_data != EEPROM_RESERVED_WORD) &&
			(eeprom_data & EEPROM_PHY_CLASS_A)) {
			ret_val = e1000_write_phy_reg(hw,
					M88E1000_PHY_PAGE_SELECT, 0x000B);
			if (ret_val)
				return ret_val;
			ret_val = e1000_write_phy_reg(hw,
					M88E1000_PHY_GEN_CONTROL, 0x8104);
			if (ret_val)
				return ret_val;

			hw->phy_reset_disable = false;
		}
	}
#endif
	return E1000_SUCCESS;
}

#ifndef CONFIG_E1000_NO_NVM
/***************************************************************************
 *
 * Obtaining software semaphore bit (SMBI) before resetting PHY.
 *
 * hw: Struct containing variables accessed by shared code
 *
 * returns: - E1000_ERR_RESET if fail to obtain semaphore.
 *            E1000_SUCCESS at any other case.
 *
 ***************************************************************************/
static int32_t
e1000_get_software_semaphore(struct e1000_hw *hw)
{
	 int32_t timeout = hw->eeprom.word_size + 1;
	 uint32_t swsm;

	DEBUGFUNC();

	if (hw->mac_type != e1000_80003es2lan && hw->mac_type != e1000_igb)
		return E1000_SUCCESS;

	while (timeout) {
		swsm = E1000_READ_REG(hw, SWSM);
		/* If SMBI bit cleared, it is now set and we hold
		 * the semaphore */
		if (!(swsm & E1000_SWSM_SMBI))
			break;
		mdelay(1);
		timeout--;
	}

	if (!timeout) {
		DEBUGOUT("Driver can't access device - SMBI bit is set.\n");
		return -E1000_ERR_RESET;
	}

	return E1000_SUCCESS;
}
#endif

/***************************************************************************
 * This function clears HW semaphore bits.
 *
 * hw: Struct containing variables accessed by shared code
 *
 * returns: - None.
 *
 ***************************************************************************/
static void
e1000_put_hw_eeprom_semaphore(struct e1000_hw *hw)
{
#ifndef CONFIG_E1000_NO_NVM
	 uint32_t swsm;

	DEBUGFUNC();

	if (!hw->eeprom_semaphore_present)
		return;

	swsm = E1000_READ_REG(hw, SWSM);
	if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
		/* Release both semaphores. */
		swsm &= ~(E1000_SWSM_SMBI | E1000_SWSM_SWESMBI);
	} else
		swsm &= ~(E1000_SWSM_SWESMBI);
	E1000_WRITE_REG(hw, SWSM, swsm);
#endif
}

/***************************************************************************
 *
 * Using the combination of SMBI and SWESMBI semaphore bits when resetting
 * adapter or Eeprom access.
 *
 * hw: Struct containing variables accessed by shared code
 *
 * returns: - E1000_ERR_EEPROM if fail to access EEPROM.
 *            E1000_SUCCESS at any other case.
 *
 ***************************************************************************/
static int32_t
e1000_get_hw_eeprom_semaphore(struct e1000_hw *hw)
{
#ifndef CONFIG_E1000_NO_NVM
	int32_t timeout;
	uint32_t swsm;

	DEBUGFUNC();

	if (!hw->eeprom_semaphore_present)
		return E1000_SUCCESS;

	if (hw->mac_type == e1000_80003es2lan || hw->mac_type == e1000_igb) {
		/* Get the SW semaphore. */
		if (e1000_get_software_semaphore(hw) != E1000_SUCCESS)
			return -E1000_ERR_EEPROM;
	}

	/* Get the FW semaphore. */
	timeout = hw->eeprom.word_size + 1;
	while (timeout) {
		swsm = E1000_READ_REG(hw, SWSM);
		swsm |= E1000_SWSM_SWESMBI;
		E1000_WRITE_REG(hw, SWSM, swsm);
		/* if we managed to set the bit we got the semaphore. */
		swsm = E1000_READ_REG(hw, SWSM);
		if (swsm & E1000_SWSM_SWESMBI)
			break;

		udelay(50);
		timeout--;
	}

	if (!timeout) {
		/* Release semaphores */
		e1000_put_hw_eeprom_semaphore(hw);
		DEBUGOUT("Driver can't access the Eeprom - "
				"SWESMBI bit is set.\n");
		return -E1000_ERR_EEPROM;
	}
#endif
	return E1000_SUCCESS;
}

/* Take ownership of the PHY */
static int32_t
e1000_swfw_sync_acquire(struct e1000_hw *hw, uint16_t mask)
{
	uint32_t swfw_sync = 0;
	uint32_t swmask = mask;
	uint32_t fwmask = mask << 16;
	int32_t timeout = 200;

	DEBUGFUNC();
	while (timeout) {
		if (e1000_get_hw_eeprom_semaphore(hw))
			return -E1000_ERR_SWFW_SYNC;

		swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
		if (!(swfw_sync & (fwmask | swmask)))
			break;

		/* firmware currently using resource (fwmask) */
		/* or other software thread currently using resource (swmask) */
		e1000_put_hw_eeprom_semaphore(hw);
		mdelay(5);
		timeout--;
	}

	if (!timeout) {
		DEBUGOUT("Driver can't access resource, SW_FW_SYNC timeout.\n");
		return -E1000_ERR_SWFW_SYNC;
	}

	swfw_sync |= swmask;
	E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);

	e1000_put_hw_eeprom_semaphore(hw);
	return E1000_SUCCESS;
}

static void e1000_swfw_sync_release(struct e1000_hw *hw, uint16_t mask)
{
	uint32_t swfw_sync = 0;

	DEBUGFUNC();
	while (e1000_get_hw_eeprom_semaphore(hw))
		; /* Empty */

	swfw_sync = E1000_READ_REG(hw, SW_FW_SYNC);
	swfw_sync &= ~mask;
	E1000_WRITE_REG(hw, SW_FW_SYNC, swfw_sync);

	e1000_put_hw_eeprom_semaphore(hw);
}

static bool e1000_is_second_port(struct e1000_hw *hw)
{
	switch (hw->mac_type) {
	case e1000_80003es2lan:
	case e1000_82546:
	case e1000_82571:
		if (E1000_READ_REG(hw, STATUS) & E1000_STATUS_FUNC_1)
			return true;
		/* Fallthrough */
	default:
		return false;
	}
}

#ifndef CONFIG_E1000_NO_NVM
/******************************************************************************
 * Reads the adapter's MAC address from the EEPROM
 *
 * hw - Struct containing variables accessed by shared code
 * enetaddr - buffering where the MAC address will be stored
 *****************************************************************************/
static int e1000_read_mac_addr_from_eeprom(struct e1000_hw *hw,
					   unsigned char enetaddr[6])
{
	uint16_t offset;
	uint16_t eeprom_data;
	int i;

	for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
		offset = i >> 1;
		if (e1000_read_eeprom(hw, offset, 1, &eeprom_data) < 0) {
			DEBUGOUT("EEPROM Read Error\n");
			return -E1000_ERR_EEPROM;
		}
		enetaddr[i] = eeprom_data & 0xff;
		enetaddr[i + 1] = (eeprom_data >> 8) & 0xff;
	}

	return 0;
}

/******************************************************************************
 * Reads the adapter's MAC address from the RAL/RAH registers
 *
 * hw - Struct containing variables accessed by shared code
 * enetaddr - buffering where the MAC address will be stored
 *****************************************************************************/
static int e1000_read_mac_addr_from_regs(struct e1000_hw *hw,
					 unsigned char enetaddr[6])
{
	uint16_t offset, tmp;
	uint32_t reg_data = 0;
	int i;

	if (hw->mac_type != e1000_igb)
		return -E1000_ERR_MAC_TYPE;

	for (i = 0; i < NODE_ADDRESS_SIZE; i += 2) {
		offset = i >> 1;

		if (offset == 0)
			reg_data = E1000_READ_REG_ARRAY(hw, RA, 0);
		else if (offset == 1)
			reg_data >>= 16;
		else if (offset == 2)
			reg_data = E1000_READ_REG_ARRAY(hw, RA, 1);
		tmp = reg_data & 0xffff;

		enetaddr[i] = tmp & 0xff;
		enetaddr[i + 1] = (tmp >> 8) & 0xff;
	}

	return 0;
}

/******************************************************************************
 * Reads the adapter's MAC address from the EEPROM and inverts the LSB for the
 * second function of dual function devices
 *
 * hw - Struct containing variables accessed by shared code
 * enetaddr - buffering where the MAC address will be stored
 *****************************************************************************/
static int e1000_read_mac_addr(struct e1000_hw *hw, unsigned char enetaddr[6])
{
	int ret_val;

	if (hw->mac_type == e1000_igb) {
		/* i210 preloads MAC address into RAL/RAH registers */
		ret_val = e1000_read_mac_addr_from_regs(hw, enetaddr);
	} else {
		ret_val = e1000_read_mac_addr_from_eeprom(hw, enetaddr);
	}
	if (ret_val)
		return ret_val;

	/* Invert the last bit if this is the second device */
	if (e1000_is_second_port(hw))
		enetaddr[5] ^= 1;

	return 0;
}
#endif

/******************************************************************************
 * Initializes receive address filters.
 *
 * hw - Struct containing variables accessed by shared code
 *
 * Places the MAC address in receive address register 0 and clears the rest
 * of the receive addresss registers. Clears the multicast table. Assumes
 * the receiver is in reset when the routine is called.
 *****************************************************************************/
static void
e1000_init_rx_addrs(struct e1000_hw *hw, unsigned char enetaddr[6])
{
	uint32_t i;
	uint32_t addr_low;
	uint32_t addr_high;

	DEBUGFUNC();

	/* Setup the receive address. */
	DEBUGOUT("Programming MAC Address into RAR[0]\n");
	addr_low = (enetaddr[0] |
		    (enetaddr[1] << 8) |
		    (enetaddr[2] << 16) | (enetaddr[3] << 24));

	addr_high = (enetaddr[4] | (enetaddr[5] << 8) | E1000_RAH_AV);

	E1000_WRITE_REG_ARRAY(hw, RA, 0, addr_low);
	E1000_WRITE_REG_ARRAY(hw, RA, 1, addr_high);

	/* Zero out the other 15 receive addresses. */
	DEBUGOUT("Clearing RAR[1-15]\n");
	for (i = 1; i < E1000_RAR_ENTRIES; i++) {
		E1000_WRITE_REG_ARRAY(hw, RA, (i << 1), 0);
		E1000_WRITE_REG_ARRAY(hw, RA, ((i << 1) + 1), 0);
	}
}

/******************************************************************************
 * Clears the VLAN filer table
 *
 * hw - Struct containing variables accessed by shared code
 *****************************************************************************/
static void
e1000_clear_vfta(struct e1000_hw *hw)
{
	uint32_t offset;

	for (offset = 0; offset < E1000_VLAN_FILTER_TBL_SIZE; offset++)
		E1000_WRITE_REG_ARRAY(hw, VFTA, offset, 0);
}

/******************************************************************************
 * Set the mac type member in the hw struct.
 *
 * hw - Struct containing variables accessed by shared code
 *****************************************************************************/
int32_t
e1000_set_mac_type(struct e1000_hw *hw)
{
	DEBUGFUNC();

	switch (hw->device_id) {
	case E1000_DEV_ID_82542:
		switch (hw->revision_id) {
		case E1000_82542_2_0_REV_ID:
			hw->mac_type = e1000_82542_rev2_0;
			break;
		case E1000_82542_2_1_REV_ID:
			hw->mac_type = e1000_82542_rev2_1;
			break;
		default:
			/* Invalid 82542 revision ID */
			return -E1000_ERR_MAC_TYPE;
		}
		break;
	case E1000_DEV_ID_82543GC_FIBER:
	case E1000_DEV_ID_82543GC_COPPER:
		hw->mac_type = e1000_82543;
		break;
	case E1000_DEV_ID_82544EI_COPPER:
	case E1000_DEV_ID_82544EI_FIBER:
	case E1000_DEV_ID_82544GC_COPPER:
	case E1000_DEV_ID_82544GC_LOM:
		hw->mac_type = e1000_82544;
		break;
	case E1000_DEV_ID_82540EM:
	case E1000_DEV_ID_82540EM_LOM:
	case E1000_DEV_ID_82540EP:
	case E1000_DEV_ID_82540EP_LOM:
	case E1000_DEV_ID_82540EP_LP:
		hw->mac_type = e1000_82540;
		break;
	case E1000_DEV_ID_82545EM_COPPER:
	case E1000_DEV_ID_82545EM_FIBER:
		hw->mac_type = e1000_82545;
		break;
	case E1000_DEV_ID_82545GM_COPPER:
	case E1000_DEV_ID_82545GM_FIBER:
	case E1000_DEV_ID_82545GM_SERDES:
		hw->mac_type = e1000_82545_rev_3;
		break;
	case E1000_DEV_ID_82546EB_COPPER:
	case E1000_DEV_ID_82546EB_FIBER:
	case E1000_DEV_ID_82546EB_QUAD_COPPER:
		hw->mac_type = e1000_82546;
		break;
	case E1000_DEV_ID_82546GB_COPPER:
	case E1000_DEV_ID_82546GB_FIBER:
	case E1000_DEV_ID_82546GB_SERDES:
	case E1000_DEV_ID_82546GB_PCIE:
	case E1000_DEV_ID_82546GB_QUAD_COPPER:
	case E1000_DEV_ID_82546GB_QUAD_COPPER_KSP3:
		hw->mac_type = e1000_82546_rev_3;
		break;
	case E1000_DEV_ID_82541EI:
	case E1000_DEV_ID_82541EI_MOBILE:
	case E1000_DEV_ID_82541ER_LOM:
		hw->mac_type = e1000_82541;
		break;
	case E1000_DEV_ID_82541ER:
	case E1000_DEV_ID_82541GI:
	case E1000_DEV_ID_82541GI_LF:
	case E1000_DEV_ID_82541GI_MOBILE:
		hw->mac_type = e1000_82541_rev_2;
		break;
	case E1000_DEV_ID_82547EI:
	case E1000_DEV_ID_82547EI_MOBILE:
		hw->mac_type = e1000_82547;
		break;
	case E1000_DEV_ID_82547GI:
		hw->mac_type = e1000_82547_rev_2;
		break;
	case E1000_DEV_ID_82571EB_COPPER:
	case E1000_DEV_ID_82571EB_FIBER:
	case E1000_DEV_ID_82571EB_SERDES:
	case E1000_DEV_ID_82571EB_SERDES_DUAL:
	case E1000_DEV_ID_82571EB_SERDES_QUAD:
	case E1000_DEV_ID_82571EB_QUAD_COPPER:
	case E1000_DEV_ID_82571PT_QUAD_COPPER:
	case E1000_DEV_ID_82571EB_QUAD_FIBER:
	case E1000_DEV_ID_82571EB_QUAD_COPPER_LOWPROFILE:
		hw->mac_type = e1000_82571;
		break;
	case E1000_DEV_ID_82572EI_COPPER:
	case E1000_DEV_ID_82572EI_FIBER:
	case E1000_DEV_ID_82572EI_SERDES:
	case E1000_DEV_ID_82572EI:
		hw->mac_type = e1000_82572;
		break;
	case E1000_DEV_ID_82573E:
	case E1000_DEV_ID_82573E_IAMT:
	case E1000_DEV_ID_82573L:
		hw->mac_type = e1000_82573;
		break;
	case E1000_DEV_ID_82574L:
		hw->mac_type = e1000_82574;
		break;
	case E1000_DEV_ID_80003ES2LAN_COPPER_SPT:
	case E1000_DEV_ID_80003ES2LAN_SERDES_SPT:
	case E1000_DEV_ID_80003ES2LAN_COPPER_DPT:
	case E1000_DEV_ID_80003ES2LAN_SERDES_DPT:
		hw->mac_type = e1000_80003es2lan;
		break;
	case E1000_DEV_ID_ICH8_IGP_M_AMT:
	case E1000_DEV_ID_ICH8_IGP_AMT:
	case E1000_DEV_ID_ICH8_IGP_C:
	case E1000_DEV_ID_ICH8_IFE:
	case E1000_DEV_ID_ICH8_IFE_GT:
	case E1000_DEV_ID_ICH8_IFE_G:
	case E1000_DEV_ID_ICH8_IGP_M:
		hw->mac_type = e1000_ich8lan;
		break;
	case PCI_DEVICE_ID_INTEL_I210_UNPROGRAMMED:
	case PCI_DEVICE_ID_INTEL_I211_UNPROGRAMMED:
	case PCI_DEVICE_ID_INTEL_I210_COPPER:
	case PCI_DEVICE_ID_INTEL_I211_COPPER:
	case PCI_DEVICE_ID_INTEL_I210_COPPER_FLASHLESS:
	case PCI_DEVICE_ID_INTEL_I210_SERDES:
	case PCI_DEVICE_ID_INTEL_I210_SERDES_FLASHLESS:
	case PCI_DEVICE_ID_INTEL_I210_1000BASEKX:
		hw->mac_type = e1000_igb;
		break;
	default:
		/* Should never have loaded on this device */
		return -E1000_ERR_MAC_TYPE;
	}
	return E1000_SUCCESS;
}

/******************************************************************************
 * Reset the transmit and receive units; mask and clear all interrupts.
 *
 * hw - Struct containing variables accessed by shared code
 *****************************************************************************/
void
e1000_reset_hw(struct e1000_hw *hw)
{
	uint32_t ctrl;
	uint32_t ctrl_ext;
	uint32_t manc;
	uint32_t pba = 0;
	uint32_t reg;

	DEBUGFUNC();

	/* get the correct pba value for both PCI and PCIe*/
	if (hw->mac_type <  e1000_82571)
		pba = E1000_DEFAULT_PCI_PBA;
	else
		pba = E1000_DEFAULT_PCIE_PBA;

	/* For 82542 (rev 2.0), disable MWI before issuing a device reset */
	if (hw->mac_type == e1000_82542_rev2_0) {
		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
#ifdef CONFIG_DM_ETH
		dm_pci_write_config16(hw->pdev, PCI_COMMAND,
				hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
#else
		pci_write_config_word(hw->pdev, PCI_COMMAND,
				hw->pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
#endif
	}

	/* Clear interrupt mask to stop board from generating interrupts */
	DEBUGOUT("Masking off all interrupts\n");
	if (hw->mac_type == e1000_igb)
		E1000_WRITE_REG(hw, I210_IAM, 0);
	E1000_WRITE_REG(hw, IMC, 0xffffffff);

	/* Disable the Transmit and Receive units.  Then delay to allow
	 * any pending transactions to complete before we hit the MAC with
	 * the global reset.
	 */
	E1000_WRITE_REG(hw, RCTL, 0);
	E1000_WRITE_REG(hw, TCTL, E1000_TCTL_PSP);
	E1000_WRITE_FLUSH(hw);

	/* The tbi_compatibility_on Flag must be cleared when Rctl is cleared. */
	hw->tbi_compatibility_on = false;

	/* Delay to allow any outstanding PCI transactions to complete before
	 * resetting the device
	 */
	mdelay(10);

	/* Issue a global reset to the MAC.  This will reset the chip's
	 * transmit, receive, DMA, and link units.  It will not effect
	 * the current PCI configuration.  The global reset bit is self-
	 * clearing, and should clear within a microsecond.
	 */
	DEBUGOUT("Issuing a global reset to MAC\n");
	ctrl = E1000_READ_REG(hw, CTRL);

	E1000_WRITE_REG(hw, CTRL, (ctrl | E1000_CTRL_RST));

	/* Force a reload from the EEPROM if necessary */
	if (hw->mac_type == e1000_igb) {
		mdelay(20);
		reg = E1000_READ_REG(hw, STATUS);
		if (reg & E1000_STATUS_PF_RST_DONE)
			DEBUGOUT("PF OK\n");
		reg = E1000_READ_REG(hw, I210_EECD);
		if (reg & E1000_EECD_AUTO_RD)
			DEBUGOUT("EEC OK\n");
	} else if (hw->mac_type < e1000_82540) {
		/* Wait for reset to complete */
		udelay(10);
		ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
		ctrl_ext |= E1000_CTRL_EXT_EE_RST;
		E1000_WRITE_REG(hw, CTRL_EXT, ctrl_ext);
		E1000_WRITE_FLUSH(hw);
		/* Wait for EEPROM reload */
		mdelay(2);
	} else {
		/* Wait for EEPROM reload (it happens automatically) */
		mdelay(4);
		/* Dissable HW ARPs on ASF enabled adapters */
		manc = E1000_READ_REG(hw, MANC);
		manc &= ~(E1000_MANC_ARP_EN);
		E1000_WRITE_REG(hw, MANC, manc);
	}

	/* Clear interrupt mask to stop board from generating interrupts */
	DEBUGOUT("Masking off all interrupts\n");
	if (hw->mac_type == e1000_igb)
		E1000_WRITE_REG(hw, I210_IAM, 0);
	E1000_WRITE_REG(hw, IMC, 0xffffffff);

	/* Clear any pending interrupt events. */
	E1000_READ_REG(hw, ICR);

	/* If MWI was previously enabled, reenable it. */
	if (hw->mac_type == e1000_82542_rev2_0) {
#ifdef CONFIG_DM_ETH
		dm_pci_write_config16(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
#else
		pci_write_config_word(hw->pdev, PCI_COMMAND, hw->pci_cmd_word);
#endif
	}
	if (hw->mac_type != e1000_igb)
		E1000_WRITE_REG(hw, PBA, pba);
}

/******************************************************************************
 *
 * Initialize a number of hardware-dependent bits
 *
 * hw: Struct containing variables accessed by shared code
 *
 * This function contains hardware limitation workarounds for PCI-E adapters
 *
 *****************************************************************************/
static void
e1000_initialize_hardware_bits(struct e1000_hw *hw)
{
	if ((hw->mac_type >= e1000_82571) &&
			(!hw->initialize_hw_bits_disable)) {
		/* Settings common to all PCI-express silicon */
		uint32_t reg_ctrl, reg_ctrl_ext;
		uint32_t reg_tarc0, reg_tarc1;
		uint32_t reg_tctl;
		uint32_t reg_txdctl, reg_txdctl1;

		/* link autonegotiation/sync workarounds */
		reg_tarc0 = E1000_READ_REG(hw, TARC0);
		reg_tarc0 &= ~((1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));

		/* Enable not-done TX descriptor counting */
		reg_txdctl = E1000_READ_REG(hw, TXDCTL);
		reg_txdctl |= E1000_TXDCTL_COUNT_DESC;
		E1000_WRITE_REG(hw, TXDCTL, reg_txdctl);

		reg_txdctl1 = E1000_READ_REG(hw, TXDCTL1);
		reg_txdctl1 |= E1000_TXDCTL_COUNT_DESC;
		E1000_WRITE_REG(hw, TXDCTL1, reg_txdctl1);


		switch (hw->mac_type) {
		case e1000_igb:			/* IGB is cool */
			return;
		case e1000_82571:
		case e1000_82572:
			/* Clear PHY TX compatible mode bits */
			reg_tarc1 = E1000_READ_REG(hw, TARC1);
			reg_tarc1 &= ~((1 << 30)|(1 << 29));

			/* link autonegotiation/sync workarounds */
			reg_tarc0 |= ((1 << 26)|(1 << 25)|(1 << 24)|(1 << 23));

			/* TX ring control fixes */
			reg_tarc1 |= ((1 << 26)|(1 << 25)|(1 << 24));

			/* Multiple read bit is reversed polarity */
			reg_tctl = E1000_READ_REG(hw, TCTL);
			if (reg_tctl & E1000_TCTL_MULR)
				reg_tarc1 &= ~(1 << 28);
			else
				reg_tarc1 |= (1 << 28);

			E1000_WRITE_REG(hw, TARC1, reg_tarc1);
			break;
		case e1000_82573:
		case e1000_82574:
			reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
			reg_ctrl_ext &= ~(1 << 23);
			reg_ctrl_ext |= (1 << 22);

			/* TX byte count fix */
			reg_ctrl = E1000_READ_REG(hw, CTRL);
			reg_ctrl &= ~(1 << 29);

			E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);
			E1000_WRITE_REG(hw, CTRL, reg_ctrl);
			break;
		case e1000_80003es2lan:
	/* improve small packet performace for fiber/serdes */
			if ((hw->media_type == e1000_media_type_fiber)
			|| (hw->media_type ==
				e1000_media_type_internal_serdes)) {
				reg_tarc0 &= ~(1 << 20);
			}

		/* Multiple read bit is reversed polarity */
			reg_tctl = E1000_READ_REG(hw, TCTL);
			reg_tarc1 = E1000_READ_REG(hw, TARC1);
			if (reg_tctl & E1000_TCTL_MULR)
				reg_tarc1 &= ~(1 << 28);
			else
				reg_tarc1 |= (1 << 28);

			E1000_WRITE_REG(hw, TARC1, reg_tarc1);
			break;
		case e1000_ich8lan:
			/* Reduce concurrent DMA requests to 3 from 4 */
			if ((hw->revision_id < 3) ||
			((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
				(hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))
				reg_tarc0 |= ((1 << 29)|(1 << 28));

			reg_ctrl_ext = E1000_READ_REG(hw, CTRL_EXT);
			reg_ctrl_ext |= (1 << 22);
			E1000_WRITE_REG(hw, CTRL_EXT, reg_ctrl_ext);

			/* workaround TX hang with TSO=on */
			reg_tarc0 |= ((1 << 27)|(1 << 26)|(1 << 24)|(1 << 23));

			/* Multiple read bit is reversed polarity */
			reg_tctl = E1000_READ_REG(hw, TCTL);
			reg_tarc1 = E1000_READ_REG(hw, TARC1);
			if (reg_tctl & E1000_TCTL_MULR)
				reg_tarc1 &= ~(1 << 28);
			else
				reg_tarc1 |= (1 << 28);

			/* workaround TX hang with TSO=on */
			reg_tarc1 |= ((1 << 30)|(1 << 26)|(1 << 24));

			E1000_WRITE_REG(hw, TARC1, reg_tarc1);
			break;
		default:
			break;
		}

		E1000_WRITE_REG(hw, TARC0, reg_tarc0);
	}
}

/******************************************************************************
 * Performs basic configuration of the adapter.
 *
 * hw - Struct containing variables accessed by shared code
 *
 * Assumes that the controller has previously been reset and is in a
 * post-reset uninitialized state. Initializes the receive address registers,
 * multicast table, and VLAN filter table. Calls routines to setup link
 * configuration and flow control settings. Clears all on-chip counters. Leaves
 * the transmit and receive units disabled and uninitialized.
 *****************************************************************************/
static int
e1000_init_hw(struct e1000_hw *hw, unsigned char enetaddr[6])
{
	uint32_t ctrl;
	uint32_t i;
	int32_t ret_val;
	uint16_t pcix_cmd_word;
	uint16_t pcix_stat_hi_word;
	uint16_t cmd_mmrbc;
	uint16_t stat_mmrbc;
	uint32_t mta_size;
	uint32_t reg_data;
	uint32_t ctrl_ext;
	DEBUGFUNC();
	/* force full DMA clock frequency for 10/100 on ICH8 A0-B0 */
	if ((hw->mac_type == e1000_ich8lan) &&
		((hw->revision_id < 3) ||
		((hw->device_id != E1000_DEV_ID_ICH8_IGP_M_AMT) &&
		(hw->device_id != E1000_DEV_ID_ICH8_IGP_M)))) {
			reg_data = E1000_READ_REG(hw, STATUS);
			reg_data &= ~0x80000000;
			E1000_WRITE_REG(hw, STATUS, reg_data);
	}
	/* Do not need initialize Identification LED */

	/* Set the media type and TBI compatibility */
	e1000_set_media_type(hw);

	/* Must be called after e1000_set_media_type
	 * because media_type is used */
	e1000_initialize_hardware_bits(hw);

	/* Disabling VLAN filtering. */
	DEBUGOUT("Initializing the IEEE VLAN\n");
	/* VET hardcoded to standard value and VFTA removed in ICH8 LAN */
	if (hw->mac_type != e1000_ich8lan) {
		if (hw->mac_type < e1000_82545_rev_3)
			E1000_WRITE_REG(hw, VET, 0);
		e1000_clear_vfta(hw);
	}

	/* For 82542 (rev 2.0), disable MWI and put the receiver into reset */
	if (hw->mac_type == e1000_82542_rev2_0) {
		DEBUGOUT("Disabling MWI on 82542 rev 2.0\n");
#ifdef CONFIG_DM_ETH
		dm_pci_write_config16(hw->pdev, PCI_COMMAND,
				      hw->
				      pci_cmd_word & ~PCI_COMMAND_INVALIDATE);
#else