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/*
* (C) Copyright 2010
* Marvell Semiconductor <www.marvell.com>
* Written-by: Prafulla Wadaskar <prafulla@marvell.com>
*
* See file CREDITS for list of people who contributed to this
* project.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; either version 2 of
* the License, or (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston,
* MA 02110-1301 USA
*/
/*
* This file contains Marvell Board Specific common defincations.
* This file should be included in board config header file.
*
* It supports common definations for Kirkwood platform
* TBD: support for Orion5X platforms
*/
#ifndef _MV_COMMON_H
#define _MV_COMMON_H
/*
* High Level Configuration Options (easy to change)
*/
#define CONFIG_MARVELL 1
#define CONFIG_ARM926EJS 1 /* Basic Architecture */
#if defined(CONFIG_KIRKWOOD)
#define CONFIG_MD5 /* get_random_hex on krikwood needs MD5 support */
#define CONFIG_KIRKWOOD_EGIGA_INIT /* Enable GbePort0/1 for kernel */
#define CONFIG_KIRKWOOD_RGMII_PAD_1V8 /* Set RGMII Pad voltage to 1.8V */
#define CONFIG_KIRKWOOD_PCIE_INIT /* Enable PCIE Port0 for kernel */
#define CONFIG_I2C_MVTWSI_BASE KW_TWSI_BASE
#define MV_UART0_BASE KW_UART0_BASE
#define MV_SATA_BASE KW_SATA_BASE
#define MV_SATA_PORT0_OFFSET KW_SATA_PORT0_OFFSET
#define MV_SATA_PORT1_OFFSET KW_SATA_PORT1_OFFSET
#else
#error "Unsupported SoC"
#endif
/* additions for new ARM relocation support */
#define CONFIG_SYS_SDRAM_BASE 0x00000000
/* Kirkwood has 2k of Security SRAM, use it for SP */
#define CONFIG_SYS_INIT_SP_ADDR 0xC8012000
/*
* CLKs configurations
*/
#define CONFIG_SYS_HZ 1000
/*
* NS16550 Configuration
*/
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE (-4)
#define CONFIG_SYS_NS16550_CLK CONFIG_SYS_TCLK
#define CONFIG_SYS_NS16550_COM1 MV_UART0_BASE
/*
* Serial Port configuration
* The following definitions let you select what serial you want to use
* for your console driver.
*/
#define CONFIG_CONS_INDEX 1 /*Console on UART0 */
#define CONFIG_BAUDRATE 115200
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \
115200,230400, 460800, 921600 }
/* auto boot */
#define CONFIG_BOOTDELAY 3 /* default enable autoboot */
/*
* For booting Linux, the board info and command line data
* have to be in the first 8 MB of memory, since this is
* the maximum mapped by the Linux kernel during initialization.
*/
#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
#define CONFIG_INITRD_TAG 1 /* enable INITRD tag */
#define CONFIG_SETUP_MEMORY_TAGS 1 /* enable memory tag */
#define CONFIG_SYS_PROMPT "Marvell>> " /* Command Prompt */
#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buff Size */
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE \
+sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buff */
/*
* NAND configuration
*/
#ifdef CONFIG_CMD_NAND
#define CONFIG_NAND_KIRKWOOD
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define NAND_MAX_CHIPS 1
#define CONFIG_SYS_NAND_BASE 0xD8000000 /* MV_DEFADR_NANDF */
#define NAND_ALLOW_ERASE_ALL 1
#define CONFIG_SYS_64BIT_VSPRINTF /* needed for nand_util.c */
#endif
/*
* SPI Flash configuration
*/
#ifdef CONFIG_CMD_SF
#define CONFIG_SPI_FLASH 1
#define CONFIG_HARD_SPI 1
#define CONFIG_KIRKWOOD_SPI 1
#define CONFIG_SPI_FLASH_MACRONIX 1
#define CONFIG_ENV_SPI_BUS 0
#define CONFIG_ENV_SPI_CS 0
#define CONFIG_ENV_SPI_MAX_HZ 50000000 /*50Mhz */
#endif
/*
* Size of malloc() pool
*/
#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* 1MiB for malloc() */
/* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_SIZE 128
/*
* Other required minimal configurations
*/
#define CONFIG_SYS_LONGHELP
#define CONFIG_AUTO_COMPLETE
#define CONFIG_CMDLINE_EDITING
#define CONFIG_CONSOLE_INFO_QUIET /* some code reduction */
#define CONFIG_ARCH_CPU_INIT /* call arch_cpu_init() */
#define CONFIG_ARCH_MISC_INIT /* call arch_misc_init() */
#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */
#define CONFIG_NR_DRAM_BANKS 4
#define CONFIG_STACKSIZE 0x00100000 /* regular stack- 1M */
#define CONFIG_SYS_LOAD_ADDR 0x00800000 /* default load adr- 8M */
#define CONFIG_SYS_MEMTEST_START 0x00400000 /* 4M */
#define CONFIG_SYS_MEMTEST_END 0x007fffff /*(_8M -1) */
#define CONFIG_SYS_RESET_ADDRESS 0xffff0000 /* Rst Vector Adr */
#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
/*
* Ethernet Driver configuration
*/
#ifdef CONFIG_CMD_NET
#define CONFIG_CMD_MII
#define CONFIG_NETCONSOLE /* include NetConsole support */
#define CONFIG_NET_MULTI /* specify more that one ports available */
#define CONFIG_MII /* expose smi ove miiphy interface */
#define CONFIG_MVGBE /* Enable Marvell Gbe Controller Driver */
#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN /* detect link using phy */
#define CONFIG_ENV_OVERWRITE /* ethaddr can be reprogrammed */
#define CONFIG_RESET_PHY_R /* use reset_phy() to init mv8831116 PHY */
#endif /* CONFIG_CMD_NET */
/*
* USB/EHCI
*/
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_EHCI /* Enable EHCI USB support */
#define CONFIG_USB_EHCI_KIRKWOOD
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_STORAGE
#define CONFIG_DOS_PARTITION
#define CONFIG_ISO_PARTITION
#define CONFIG_SUPPORT_VFAT
#endif /* CONFIG_CMD_USB */
/*
* IDE Support on SATA ports
*/
#ifdef CONFIG_CMD_IDE
#define __io
#define CONFIG_CMD_EXT2
#define CONFIG_MVSATA_IDE
#define CONFIG_IDE_PREINIT
#define CONFIG_MVSATA_IDE_USE_PORT1
/* Needs byte-swapping for ATA data register */
#define CONFIG_IDE_SWAP_IO
/* Data, registers and alternate blocks are at the same offset */
#define CONFIG_SYS_ATA_DATA_OFFSET (0x0100)
#define CONFIG_SYS_ATA_REG_OFFSET (0x0100)
#define CONFIG_SYS_ATA_ALT_OFFSET (0x0100)
/* Each 8-bit ATA register is aligned to a 4-bytes address */
#define CONFIG_SYS_ATA_STRIDE 4
/* Controller supports 48-bits LBA addressing */
#define CONFIG_LBA48
/* CONFIG_CMD_IDE requires some #defines for ATA registers */
#define CONFIG_SYS_IDE_MAXBUS 2
#define CONFIG_SYS_IDE_MAXDEVICE 2
/* ATA registers base is at SATA controller base */
#define CONFIG_SYS_ATA_BASE_ADDR MV_SATA_BASE
#endif /* CONFIG_CMD_IDE */
/*
* I2C related stuff
*/
#ifdef CONFIG_CMD_I2C
#define CONFIG_I2C_MVTWSI
#define CONFIG_SYS_I2C_SLAVE 0x0
#define CONFIG_SYS_I2C_SPEED 100000
#endif
/*
* File system
*/
#define CONFIG_CMD_EXT2
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_FAT
#define CONFIG_CMD_UBI
#define CONFIG_CMD_UBIFS
#define CONFIG_RBTREE
#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */
#define CONFIG_MTD_PARTITIONS
#define CONFIG_CMD_MTDPARTS
#define CONFIG_LZO
#endif /* _MV_COMMON_H */
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