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/* SPDX-License-Identifier: GPL-2.0+ */
/*
* Copyright 2018-2020 NXP
*/
#ifndef __LX2_QDS_H
#define __LX2_QDS_H
#include "lx2160a_common.h"
/* Qixis */
#define QIXIS_XMAP_MASK 0x07
#define QIXIS_XMAP_SHIFT 5
#define QIXIS_RST_CTL_RESET_EN 0x30
#define QIXIS_LBMAP_DFLTBANK 0x00
#define QIXIS_LBMAP_ALTBANK 0x20
#define QIXIS_LBMAP_QSPI 0x00
#define QIXIS_RCW_SRC_QSPI 0xff
#define QIXIS_RST_CTL_RESET 0x31
#define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20
#define QIXIS_RCFG_CTL_RECONFIG_START 0x21
#define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08
#define QIXIS_LBMAP_MASK 0x0f
#define QIXIS_LBMAP_SD
#define QIXIS_LBMAP_EMMC
#define QIXIS_RCW_SRC_SD 0x08
#define QIXIS_RCW_SRC_EMMC 0x09
#define NON_EXTENDED_DUTCFG
#define QIXIS_SDID_MASK 0x07
#define QIXIS_ESDHC_NO_ADAPTER 0x7
/* SYSCLK */
#define QIXIS_SYSCLK_100 0x0
#define QIXIS_SYSCLK_125 0x1
#define QIXIS_SYSCLK_133 0x2
/* DDRCLK */
#define QIXIS_DDRCLK_100 0x0
#define QIXIS_DDRCLK_125 0x1
#define QIXIS_DDRCLK_133 0x2
#define BRDCFG4_EMI1SEL_MASK 0xF8
#define BRDCFG4_EMI1SEL_SHIFT 3
#define BRDCFG4_EMI2SEL_MASK 0x07
#define BRDCFG4_EMI2SEL_SHIFT 0
/* VID */
#define I2C_MUX_CH_VOL_MONITOR 0xA
/* Voltage monitor on channel 2*/
#define I2C_VOL_MONITOR_ADDR 0x63
#define I2C_VOL_MONITOR_BUS_V_OFFSET 0x2
#define I2C_VOL_MONITOR_BUS_V_OVF 0x1
#define I2C_VOL_MONITOR_BUS_V_SHIFT 3
#define CONFIG_VID_FLS_ENV "lx2160aqds_vdd_mv"
#define CONFIG_VID
/* The lowest and highest voltage allowed*/
#define VDD_MV_MIN 775
#define VDD_MV_MAX 925
/* PM Bus commands code for LTC3882*/
#define PMBUS_CMD_PAGE 0x0
#define PMBUS_CMD_READ_VOUT 0x8B
#define PMBUS_CMD_PAGE_PLUS_WRITE 0x05
#define PMBUS_CMD_VOUT_COMMAND 0x21
#define PWM_CHANNEL0 0x0
#define CONFIG_VOL_MONITOR_LTC3882_SET
#define CONFIG_VOL_MONITOR_LTC3882_READ
/* RTC */
#define CONFIG_SYS_RTC_BUS_NUM 0
#define I2C_MUX_CH_RTC 0xB
/*
* MMC
*/
#ifdef CONFIG_MMC
#ifndef __ASSEMBLY__
u8 qixis_esdhc_detect_quirk(void);
#endif
#define CONFIG_ESDHC_DETECT_QUIRK qixis_esdhc_detect_quirk()
#endif
/* MAC/PHY configuration */
#if defined(CONFIG_FSL_MC_ENET)
#define CONFIG_MII
#define CONFIG_ETHPRIME "DPMAC17@rgmii-id"
#define AQ_PHY_ADDR1 0x00
#define AQ_PHY_ADDR2 0x01
#define AQ_PHY_ADDR3 0x02
#define AQ_PHY_ADDR4 0x03
#define CORTINA_NO_FW_UPLOAD
#define CORTINA_PHY_ADDR1 0x0
#define INPHI_PHY_ADDR1 0x0
#define INPHI_PHY_ADDR2 0x1
#define RGMII_PHY_ADDR1 0x01
#define RGMII_PHY_ADDR2 0x02
#define SGMII_CARD_PORT1_PHY_ADDR 0x1C
#define SGMII_CARD_PORT2_PHY_ADDR 0x1D
#define SGMII_CARD_PORT3_PHY_ADDR 0x1E
#define SGMII_CARD_PORT4_PHY_ADDR 0x1F
#endif
/* EEPROM */
#define CONFIG_ID_EEPROM
#define CONFIG_SYS_I2C_EEPROM_NXID
#define CONFIG_SYS_EEPROM_BUS_NUM 0
#define CONFIG_SYS_I2C_EEPROM_ADDR 0x57
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
/* Initial environment variables */
#define CONFIG_EXTRA_ENV_SETTINGS \
EXTRA_ENV_SETTINGS \
"boot_scripts=lx2160aqds_boot.scr\0" \
"boot_script_hdr=hdr_lx2160aqds_bs.out\0" \
"BOARD=lx2160aqds\0" \
"xspi_bootcmd=echo Trying load from flexspi..;" \
"sf probe 0:0 && sf read $load_addr " \
"$kernel_start $kernel_size ; env exists secureboot &&" \
"sf read $kernelheader_addr_r $kernelheader_start " \
"$kernelheader_size && esbc_validate ${kernelheader_addr_r}; "\
" bootm $load_addr#$BOARD\0" \
"sd_bootcmd=echo Trying load from sd card..;" \
"mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$BOARD\0" \
"sd2_bootcmd=echo Trying load from emmc card..;" \
"mmc dev 1; mmcinfo; mmc read $load_addr " \
"$kernel_addr_sd $kernel_size_sd ;" \
"env exists secureboot && mmc read $kernelheader_addr_r "\
"$kernelhdr_addr_sd $kernelhdr_size_sd " \
" && esbc_validate ${kernelheader_addr_r};" \
"bootm $load_addr#$BOARD\0"
#include <asm/fsl_secure_boot.h>
#endif /* __LX2_QDS_H */
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