blob: 32f59fd8f7148e0dcc7ba4f9917bf7017a0949b8 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
|
// SPDX-License-Identifier: GPL-2.0
/*
* Copyright (C) 2019 Intel Corporation <www.intel.com>
*/
#ifndef __CACHE_H
#define __CACHE_H
/*
* Structure for the cache controller
*/
struct cache_info {
phys_addr_t base; /* Base physical address of cache device. */
};
struct cache_ops {
/**
* get_info() - Get basic cache info
*
* @dev: Device to check (UCLASS_CACHE)
* @info: Place to put info
* @return 0 if OK, -ve on error
*/
int (*get_info)(struct udevice *dev, struct cache_info *info);
/**
* enable() - Enable cache
*
* @dev: Device to check (UCLASS_CACHE)
* @return 0 if OK, -ve on error
*/
int (*enable)(struct udevice *dev);
/**
* disable() - Flush and disable cache
*
* @dev: Device to check (UCLASS_CACHE)
* @return 0 if OK, -ve on error
*/
int (*disable)(struct udevice *dev);
};
#define cache_get_ops(dev) ((struct cache_ops *)(dev)->driver->ops)
/**
* cache_get_info() - Get information about a cache controller
*
* @dev: Device to check (UCLASS_CACHE)
* @info: Returns cache info
* @return 0 if OK, -ve on error
*/
int cache_get_info(struct udevice *dev, struct cache_info *info);
/**
* cache_enable() - Enable cache
*
* @dev: Device to check (UCLASS_CACHE)
* @return 0 if OK, -ve on error
*/
int cache_enable(struct udevice *dev);
/**
* cache_disable() - Flush and disable cache
*
* @dev: Device to check (UCLASS_CACHE)
* @return 0 if OK, -ve on error
*/
int cache_disable(struct udevice *dev);
#endif
|
