1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
|
// SPDX-License-Identifier: GPL-2.0+
/*
* Copyright (C) 2007 Freescale Semiconductor, Inc.
*
* Author: Scott Wood <scottwood@freescale.com>
* Dave Liu <daveliu@freescale.com>
*/
#include <common.h>
#include <hwconfig.h>
#include <i2c.h>
#include <init.h>
#include <net.h>
#include <linux/delay.h>
#include <linux/libfdt.h>
#include <fdt_support.h>
#include <pci.h>
#include <mpc83xx.h>
#include <netdev.h>
#include <asm/io.h>
#include <ns16550.h>
#include <nand.h>
DECLARE_GLOBAL_DATA_PTR;
int board_early_init_f(void)
{
volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
gd->flags |= GD_FLG_SILENT;
return 0;
}
#ifndef CONFIG_NAND_SPL
static u8 read_board_info(void)
{
u8 val8;
i2c_set_bus_num(0);
if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
return val8;
else
return 0;
}
int checkboard(void)
{
static const char * const rev_str[] = {
"0.0",
"0.1",
"1.0",
"1.1",
"<unknown>",
};
u8 info;
int i;
info = read_board_info();
i = (!info) ? 4: info & 0x03;
printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
return 0;
}
static struct pci_region pci_regions[] = {
{
bus_start: CONFIG_SYS_PCI_MEM_BASE,
phys_start: CONFIG_SYS_PCI_MEM_PHYS,
size: CONFIG_SYS_PCI_MEM_SIZE,
flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
},
{
bus_start: CONFIG_SYS_PCI_MMIO_BASE,
phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
size: CONFIG_SYS_PCI_MMIO_SIZE,
flags: PCI_REGION_MEM
},
{
bus_start: CONFIG_SYS_PCI_IO_BASE,
phys_start: CONFIG_SYS_PCI_IO_PHYS,
size: CONFIG_SYS_PCI_IO_SIZE,
flags: PCI_REGION_IO
}
};
static struct pci_region pcie_regions_0[] = {
{
.bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
.size = CONFIG_SYS_PCIE1_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE1_IO_BASE,
.phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
.size = CONFIG_SYS_PCIE1_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
static struct pci_region pcie_regions_1[] = {
{
.bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
.phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
.size = CONFIG_SYS_PCIE2_MEM_SIZE,
.flags = PCI_REGION_MEM,
},
{
.bus_start = CONFIG_SYS_PCIE2_IO_BASE,
.phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
.size = CONFIG_SYS_PCIE2_IO_SIZE,
.flags = PCI_REGION_IO,
},
};
void pci_init_board(void)
{
volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
volatile sysconf83xx_t *sysconf = &immr->sysconf;
volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
volatile law83xx_t *pcie_law = sysconf->pcielaw;
struct pci_region *reg[] = { pci_regions };
struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
/* Enable all 3 PCI_CLK_OUTPUTs. */
clk->occr |= 0xe0000000;
/*
* Configure PCI Local Access Windows
*/
pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
mpc83xx_pci_init(1, reg);
/* Configure the clock for PCIE controller */
clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
/* Deassert the resets in the control register */
out_be32(&sysconf->pecr1, 0xE0008000);
out_be32(&sysconf->pecr2, 0xE0008000);
udelay(2000);
/* Configure PCI Express Local Access Windows */
out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
mpc83xx_pcie_init(2, pcie_reg);
}
#if defined(CONFIG_OF_BOARD_SETUP)
void fdt_tsec1_fixup(void *fdt, struct bd_info *bd)
{
const char disabled[] = "disabled";
const char *path;
int ret;
if (hwconfig_arg_cmp("board_type", "tsec1")) {
return;
} else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
printf("NOTICE: No or unknown board_type hwconfig specified.\n"
" Assuming board with TSEC1.\n");
return;
}
ret = fdt_path_offset(fdt, "/aliases");
if (ret < 0) {
printf("WARNING: can't find /aliases node\n");
return;
}
path = fdt_getprop(fdt, ret, "ethernet0", NULL);
if (!path) {
printf("WARNING: can't find ethernet0 alias\n");
return;
}
do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
}
int ft_board_setup(void *blob, struct bd_info *bd)
{
ft_cpu_setup(blob, bd);
#ifdef CONFIG_PCI
ft_pci_setup(blob, bd);
#endif
fsl_fdt_fixup_dr_usb(blob, bd);
fdt_tsec1_fixup(blob, bd);
return 0;
}
#endif
int board_eth_init(struct bd_info *bis)
{
cpu_eth_init(bis); /* Initialize TSECs first */
return pci_eth_init(bis);
}
#else /* CONFIG_NAND_SPL */
int checkboard(void)
{
puts("Board: Freescale MPC8315ERDB\n");
return 0;
}
void board_init_f(ulong bootflag)
{
board_early_init_f();
ns16550_init((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500),
CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
puts("NAND boot... ");
timer_init();
dram_init();
relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
CONFIG_SYS_NAND_U_BOOT_RELOC);
}
void board_init_r(gd_t *gd, ulong dest_addr)
{
nand_boot();
}
void putc(char c)
{
if (gd->flags & GD_FLG_SILENT)
return;
if (c == '\n')
ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), '\r');
ns16550_putc((struct ns16550 *)(CONFIG_SYS_IMMR + 0x4500), c);
}
#endif /* CONFIG_NAND_SPL */
|
