blob: 844f7e94f13eb1dd852a4fa9eafd0642ded102f0 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
|
/*
* (C) Copyright 2006
* Wolfgang Denk, DENX Software Engineering, wd@denx.de
*
* Copyright 2009 Freescale Semiconductor, Inc.
*
* SPDX-License-Identifier: GPL-2.0+
*/
#include "config.h" /* CONFIG_BOARDDIR */
OUTPUT_ARCH(powerpc)
SECTIONS
{
. = 0xfff00000;
.text : {
*(.text*)
}
_etext = .;
.reloc : {
_GOT2_TABLE_ = .;
KEEP(*(.got2))
KEEP(*(.got))
PROVIDE(_GLOBAL_OFFSET_TABLE_ = . + 4);
_FIXUP_TABLE_ = .;
KEEP(*(.fixup))
}
__got2_entries = ((_GLOBAL_OFFSET_TABLE_ - _GOT2_TABLE_) >> 2) - 1;
__fixup_entries = (. - _FIXUP_TABLE_) >> 2;
. = ALIGN(8);
.data : {
*(.rodata*)
*(.data*)
*(.sdata*)
}
_edata = .;
.u_boot_list : {
KEEP(*(SORT(.u_boot_list*)));
}
. = ALIGN(8);
__init_begin = .;
__init_end = .;
#if defined(CONFIG_FSL_IFC) /* Restrict bootpg at 4K boundry for IFC */
.bootpg ADDR(.text) + 0x1000 :
{
start.o (.bootpg)
}
#define RESET_VECTOR_OFFSET 0x1ffc /* IFC has 8K sram */
#elif defined(CONFIG_FSL_ELBC)
#define RESET_VECTOR_OFFSET 0xffc /* LBC has 4k sram */
#else
#error unknown NAND controller
#endif
.resetvec ADDR(.text) + RESET_VECTOR_OFFSET : {
KEEP(*(.resetvec))
} = 0xffff
__bss_start = .;
.bss : {
*(.sbss*)
*(.bss*)
}
__bss_end = .;
}
ASSERT(__init_end <= (0xfff00000 + RESET_VECTOR_OFFSET), "NAND bootstrap too big");
|
