blob: 6a6e7467a233be65b18dc9bde24a4d103f080520 (
plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
|
// SPDX-License-Identifier: GPL-2.0
/*
* dts file for Xilinx Versal Mini eMMC0 Configuration
*
* (C) Copyright 2018-2019, Xilinx, Inc.
*
* Siva Durga Prasad <siva.durga.paladugu@xilinx.com>
* Michal Simek <michal.simek@xilinx.com>
*/
/dts-v1/;
/ {
compatible = "xlnx,versal";
#address-cells = <2>;
#size-cells = <2>;
model = "Xilinx Versal MINI eMMC0";
clk200: clk200 {
compatible = "fixed-clock";
#clock-cells = <0x0>;
clock-frequency = <200000000>;
};
dcc: dcc {
compatible = "arm,dcc";
status = "okay";
u-boot,dm-pre-reloc;
};
amba: amba {
u-boot,dm-pre-reloc;
compatible = "simple-bus";
#address-cells = <0x2>;
#size-cells = <0x2>;
ranges;
sdhci0: sdhci@f1040000 {
compatible = "xlnx,versal-8.9a", "arasan,sdhci-8.9a";
status = "okay";
non-removable;
disable-wp;
bus-width = <8>;
reg = <0x0 0xf1040000 0x0 0x10000>;
clock-names = "clk_xin", "clk_ahb";
clocks = <&clk200 &clk200>;
xlnx,device_id = <0>;
no-1-8-v;
xlnx,mio-bank = <0>;
#stream-id-cells = <1>;
};
};
aliases {
serial0 = &dcc;
mmc0 = &sdhci0;
};
chosen {
stdout-path = "serial0:115200";
};
memory@0 {
device_type = "memory";
reg = <0x0 0x0 0x0 0x20000000>;
};
};
|
