1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
|
// SPDX-License-Identifier: GPL-2.0+ OR BSD-3-Clause
/*
* Copyright : STMicroelectronics 2018
*/
/ {
aliases {
gpio0 = &gpioa;
gpio1 = &gpiob;
gpio2 = &gpioc;
gpio3 = &gpiod;
gpio4 = &gpioe;
gpio5 = &gpiof;
gpio6 = &gpiog;
gpio7 = &gpioh;
gpio8 = &gpioi;
gpio9 = &gpioj;
gpio10 = &gpiok;
gpio25 = &gpioz;
pinctrl0 = &pinctrl;
pinctrl1 = &pinctrl_z;
};
clocks {
u-boot,dm-pre-reloc;
};
/* need PSCI for sysreset during board_f */
psci {
u-boot,dm-pre-proper;
};
reboot {
u-boot,dm-pre-reloc;
compatible = "syscon-reboot";
regmap = <&rcc>;
offset = <0x404>;
mask = <0x1>;
};
soc {
u-boot,dm-pre-reloc;
ddr: ddr@5a003000 {
u-boot,dm-pre-reloc;
compatible = "st,stm32mp1-ddr";
reg = <0x5A003000 0x550
0x5A004000 0x234>;
clocks = <&rcc AXIDCG>,
<&rcc DDRC1>,
<&rcc DDRC2>,
<&rcc DDRPHYC>,
<&rcc DDRCAPB>,
<&rcc DDRPHYCAPB>;
clock-names = "axidcg",
"ddrc1",
"ddrc2",
"ddrphyc",
"ddrcapb",
"ddrphycapb";
status = "okay";
};
};
};
&bsec {
u-boot,dm-pre-reloc;
};
&clk_csi {
u-boot,dm-pre-reloc;
};
&clk_hsi {
u-boot,dm-pre-reloc;
};
&clk_hse {
u-boot,dm-pre-reloc;
};
&clk_lsi {
u-boot,dm-pre-reloc;
};
&clk_lse {
u-boot,dm-pre-reloc;
};
&cpu0_opp_table {
u-boot,dm-spl;
opp-650000000 {
u-boot,dm-spl;
};
opp-800000000 {
u-boot,dm-spl;
};
};
&gpioa {
u-boot,dm-pre-reloc;
};
&gpiob {
u-boot,dm-pre-reloc;
};
&gpioc {
u-boot,dm-pre-reloc;
};
&gpiod {
u-boot,dm-pre-reloc;
};
&gpioe {
u-boot,dm-pre-reloc;
};
&gpiof {
u-boot,dm-pre-reloc;
};
&gpiog {
u-boot,dm-pre-reloc;
};
&gpioh {
u-boot,dm-pre-reloc;
};
&gpioi {
u-boot,dm-pre-reloc;
};
&gpioj {
u-boot,dm-pre-reloc;
};
&gpiok {
u-boot,dm-pre-reloc;
};
&gpioz {
u-boot,dm-pre-reloc;
};
&iwdg2 {
u-boot,dm-pre-reloc;
};
/* pre-reloc probe = reserve video frame buffer in video_reserve() */
<dc {
u-boot,dm-pre-proper;
};
/* temp = waiting kernel update */
&m4_rproc {
resets = <&rcc MCU_R>,
<&rcc MCU_HOLD_BOOT_R>;
reset-names = "mcu_rst", "hold_boot";
};
&pinctrl {
u-boot,dm-pre-reloc;
};
&pinctrl_z {
u-boot,dm-pre-reloc;
};
&pwr_regulators {
u-boot,dm-pre-reloc;
};
&rcc {
u-boot,dm-pre-reloc;
#address-cells = <1>;
#size-cells = <0>;
};
&sdmmc1 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&sdmmc2 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&sdmmc3 {
compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell";
};
&usart1 {
resets = <&rcc USART1_R>;
};
&usart2 {
resets = <&rcc USART2_R>;
};
&usart3 {
resets = <&rcc USART3_R>;
};
&uart4 {
resets = <&rcc UART4_R>;
};
&uart5 {
resets = <&rcc UART5_R>;
};
&usart6 {
resets = <&rcc USART6_R>;
};
&uart7 {
resets = <&rcc UART7_R>;
};
&uart8{
resets = <&rcc UART8_R>;
};
|
