summaryrefslogtreecommitdiffstats
path: root/arch/arm/dts/armada-7040-db-nand.dts
blob: f249c71f6561bdbebc4eb243c0d45075d36b06b6 (plain)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
// SPDX-License-Identifier: GPL-2.0+
/*
 * Copyright (C) 2016- 2021 Marvell International Ltd.
 */

/*
 * Device Tree file for Marvell Armada 7040 Development board platform
 * Boot device: NAND, 0xE (SW3)
 */

#include "armada-7040.dtsi"

/ {
	model = "Marvell Armada 7040 DB board with NAND";
	compatible = "marvell,armada7040-db-nand", "marvell,armada7040-db",
		     "marvell,armada7040", "marvell,armada-ap806-quad",
		     "marvell,armada-ap806";

	chosen {
		stdout-path = "serial0:115200n8";
	};

	aliases {
		i2c0 = &cp0_i2c0;
		spi0 = &cp0_spi1;
	};

	memory@00000000 {
		device_type = "memory";
		reg = <0x0 0x0 0x0 0x80000000>;
	};
};

&ap_pinctl {
	   /* MPP Bus:
	    * SDIO  [0-5]
	    * UART0 [11,19]
	    */
		  /* 0   1   2   3   4   5   6   7   8   9 */
	pin-func = < 0x1 0x1 0x1 0x1 0x1 0x1 0x0 0x0 0x0 0x0
		     0x0 0x3 0x0 0x0 0x0 0x0 0x0 0x0 0x0 0x3 >;
};

&uart0 {
	status = "okay";
};


&cp0_pcie2 {
	status = "okay";
};

&cp0_i2c0 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_i2c0_pins>;
	status = "okay";
	clock-frequency = <100000>;
};

&cp0_pinctl {
		/* MPP Bus:
		 * AUDIO   [0-5]
                 * GBE     [6-11]
		 * SS_PWDN [12]
		 * NF_RBn  [13]
                 * GPIO    [14]
		 * DEV_BUS [15-27]
		 * SATA1   [28]
		 * UART0   [29-30]
		 * MSS_VTT_EN [31]
		 * SMI	   [32,34]
		 * XSMI    [35-36]
		 * I2C	   [37-38]
		 * RGMII1  [44-55]
		 * SD	   [56-61]
		 * GPIO    [62]
		 */
		 /*   0   1   2   3   4   5   6   7   8   9 */
	 pin-func = < 0x2 0x2 0x2 0x2 0x2 0x2 0x3 0x3 0x3 0x3
		      0x3 0x3 0x0 0x2 0x0 0x1 0x1 0x1 0x1 0x1
		      0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x1 0x9 0xa
		      0xa 0x0 0x7 0x0 0x7 0x7 0x7 0x2 0x2 0x0
		      0x0 0x0 0x0 0x0 0x1 0x1 0x1 0x1 0x1 0x1
		      0x1 0x1 0x1 0x1 0x1 0x1 0xe 0xe 0xe 0xe
		      0xe 0xe 0x0>;
};

&cp0_spi1 {
	pinctrl-names = "default";
	pinctrl-0 = <&cp0_spi0_pins>;
	status = "disabled";

	spi-flash@0 {
		#address-cells = <0x1>;
		#size-cells = <0x1>;
		compatible = "jedec,spi-nor";
		reg = <0x0>;
		spi-max-frequency = <20000000>;

		partitions {
			compatible = "fixed-partitions";
			#address-cells = <1>;
			#size-cells = <1>;

			partition@0 {
				label = "U-Boot";
				reg = <0x0 0x200000>;
			};

			partition@400000 {
				label = "Filesystem";
				reg = <0x200000 0xe00000>;
			};
		};
	};
};

&cp0_sata0 {
	status = "okay";
};

&cp0_usb3_0 {
	status = "okay";
};

&cp0_usb3_1 {
	status = "okay";
};

&cp0_comphy {
	phy0 {
		phy-type = <PHY_TYPE_SGMII2>;
		phy-speed = <PHY_SPEED_3_125G>;
	};

	phy1 {
		phy-type = <PHY_TYPE_USB3_HOST0>;
		phy-speed = <PHY_SPEED_5G>;
	};

	phy2 {
		phy-type = <PHY_TYPE_SGMII0>;
		phy-speed = <PHY_SPEED_1_25G>;
	};

	phy3 {
		phy-type = <PHY_TYPE_SATA1>;
		phy-speed = <PHY_SPEED_5G>;
	};

	phy4 {
		phy-type = <PHY_TYPE_USB3_HOST1>;
		phy-speed = <PHY_SPEED_5G>;
	};

	phy5 {
		phy-type = <PHY_TYPE_PEX2>;
		phy-speed = <PHY_SPEED_5G>;
	};
};

&cp0_nand {
	status = "okay";
};

&cp0_utmi0 {
	status = "okay";
};

&cp0_utmi1 {
	status = "okay";
};

&ap_sdhci0 {
	status = "okay";
	bus-width = <4>;
	no-1-8-v;
	non-removable;
};

&cp0_sdhci0 {
	status = "okay";
	bus-width = <4>;
	no-1-8-v;
	non-removable;
};