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* armv8: ls1028ardb: add xspi parameter to qixis commandYuantian Tang2020-07-271-2/+2
| | | | | | | | Add xspi boot source to qixis command to let the soc boot from flex-nor flash chip. Signed-off-by: Yuantian Tang <andy.tang@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* include/configs: ls1012a: Remove fdt_high env variableUdit Agarwal2020-07-275-5/+5
| | | | | | | | | Remove "fdt_high" environment variable to use the bootm_size to safely contain a kernel, device tree and initrd for relocation. Signed-off-by: Udit Agarwal <udit.agarwal@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* I2C: ls1043a, ls1046a: enable SYS_I2C_MXCBiwen Li2020-07-272-3/+1
| | | | | | | | | This enables SYS_I2C_MXC to fix a bug that failed to boot from sd card with image u-boot-with-spl-pbl.bin Signed-off-by: Biwen Li <biwen.li@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: layerscape: properly use CPU_RELEASE_ADDRMichael Walle2020-07-276-6/+6
| | | | | | | | | | | | The generic armv8 code already has support to bring up the secondary cores. Thus, don't hardcode the jump in the layerscape lowlevel_init to the spin table code; instead just return early and let the common armv8 code handle the jump. This way we can actually use the CPU_RELEASE_ADDR feature. Signed-off-by: Michael Walle <michael@walle.cc> [Rebased, Removed kontron_sl28.h change as file does not exist] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: pfe_eth: Use spi_flash_read API to access flash memoryKuldeep Singh2020-07-271-1/+4
| | | | | | | | | | Current PFE firmware access spi-nor memory directly. New spi-mem framework does not support direct memory access. So, let's use spi_flash_read API to access memory instead of directly using it. Signed-off-by: Kuldeep Singh <kuldeep.singh@nxp.com> Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* configs: ls1088ardb: Add support for usb boot targetEra Tiwari2020-07-271-0/+1
| | | | | | | | | | | LS1088A-RDB has MMC, SCSI, DHCP as boot targets, but the USB support was missing. Add support for USB as Boot_targets_devices. Signed-off-by: Era Tiwari <era.tiwari@nxp.com> Signed-off-by: Pramod Kumar <pramod.kumar_1@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* armv8: ls1028a: move FSL_LAYERSCAPE to kconfigMichael Walle2020-07-271-1/+0
| | | | | | | | | | CONFIG_FSL_LAYERSCAPE is available in kconfig. There is no need to define it per board; the ls1028a_common.h is really board dependent and only fits to the NXP eval boards. Instead select CONFIG_FSL_LAYERSCAPE when ARCH_LS1028A is selected. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* fsl_dspi: Introduce DT bindings for CS-SCK and SCK-CS delaysVladimir Oltean2020-07-271-0/+1
| | | | | | | | | | | | | | Communication with some SPI slaves just won't cut it if these delays (before the beginning, and after the end of a transfer) are not added to the Chip Select signal. These are a straight copy from Linux: Documentation/devicetree/bindings/spi/spi-fsl-dspi.txt drivers/spi/spi-fsl-dspi.c Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2020-07-241-1/+6
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fix SiFive HiFive Unleashed board booting failure problem. - Enable SiFive fu540 PWM driver. - Support SiFive fu540: SPI boot. - Update OpenSBI used for RISC-V CI testing. - Revert "riscv: Allow use of reset drivers". - Revert "Revert "riscv: sifive: fu540: Add gpio-restart support"". - sysreset: syscon: - Don't assume default value for offset and mask property. - Support value property. - qemu: Add syscon reboot and poweroff support. - Fix SIFIVE debug serial dependency. - Fix linking error when building u-boot-spl with no SMP support. - AE350 use fdtdec_get_addr_size_auto_noparent to parse smc reg. - Make memory node available to SPL in hifive-unleashed-a00-u-boot.dtsi - SiFive fu540 avoid using hardcoded ram base and size.
| * sifive: fu540: Enable SF distro bootcmdJagan Teki2020-07-241-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable SPI flash(SF) distro boot command in Sifive FU540. This distro boot will read the boot script at specific location at the flash and start sourcing the same. Included the SF device at the last of the target devices list since all the rest of the devices on the list have more possibility to boot the distribution due to the size of the SPI flash is concern. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
| * sifive: fu540: Add boot flash script offset, sizeJagan Teki2020-07-241-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | HiFive-Unleashed-A00 has SPI flash with 32MiB size. So, let's use the script offset at the end of 4K. This way it cannot overlap any offsets being used by software components in flash layout. So, SF distrocmd will pick the script at desired script address and run. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bin.meng@windriver.com>
* | Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2020-07-244-154/+47
|/ | | | | | | | | | This reverts commit 5d3a21df6694ebd66d5c34c9d62a26edc7456fc7, reversing changes made to 56d37f1c564107e27d873181d838571b7d7860e7. Unfortunately this is causing CI failures: https://travis-ci.org/github/trini/u-boot/jobs/711313649 Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dmTom Rini2020-07-234-47/+154
|\ | | | | | | | | | | | | | | binman support for FIT new UCLASS_SOC patman switch 'test' command minor fdt fixes patman usability improvements
| * dm: soc: Introduce UCLASS_SOC for SOC ID and attribute matchingDave Gerlach2020-07-202-0/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce UCLASS_SOC to be used for SOC identification and attribute matching based on the SoC ID info. This allows drivers to be provided for SoCs to retrieve SoC identifying information and also for matching device attributes for selecting SoC specific data. This is useful for other device drivers that may need different parameters or quirks enabled depending on the specific device variant in use. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * Revert "lib: fdt: Split fdtdec_setup_mem_size_base()"Michal Simek2020-07-201-20/+0
| | | | | | | | | | | | | | | | | | This reverts commit 3ebe09d09a407f93022d945a205c5318239eb3f6. There is no user of this split function that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * Revert "lib: fdt: Split fdtdec_setup_memory_banksize()"Michal Simek2020-07-201-19/+0
| | | | | | | | | | | | | | | | | | This reverts commit 118f4d4559a4386fa87a1e2509e84a1986b24a34. There is no user of this split function that's why remove it. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Simon Glass <sjg@chromium.org>
| * cpu: Convert the methods to use a const udevice *Simon Glass2020-07-201-8/+8
| | | | | | | | | | | | | | These functions should not modify the device. Convert them to const so that callers don't need to cast if they have a const udevice *. Signed-off-by: Simon Glass <sjg@chromium.org>
* | Merge tag 'efi-2020-10-rc1-5' of ↵Tom Rini2020-07-233-10/+17
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-efi Pull request for UEFI sub-system for efi-2020-10-rc1 (5) The series provides bug fixes for: * crash in OS when accessing UEFI variables * returning from UEFI fit images to U-Boot * error handling for variable services provided by OP-TEE * error handling in EFI_FILE_PROTOCOL.Read() * missing function documentation The first patches needed to use intermediate certificates for secure boot are added. (The rest of the series requires updating sbsigntool in our CI systems.) Logging is enabled in the bootefi command.
| * | lib: crypto: export and enhance pkcs7_verify_one()AKASHI Takahiro2020-07-221-1/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The function, pkcs7_verify_one(), will be utilized to rework signature verification logic aiming to support intermediate certificates in "chain of trust." To do that, its function interface is expanded, adding an extra argument which is expected to return the last certificate in trusted chain. Then, this last one must further be verified with signature database, db and/or dbx. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
| * | lib: crypto: add public_key_verify_signature()AKASHI Takahiro2020-07-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function will be called from x509_check_for_self_signed() and pkcs7_verify_one(), which will be imported from linux in a later patch. While it does exist in linux code and has a similar functionality of rsa_verify(), it calls further linux-specific interfaces inside. That could lead to more files being imported from linux. So simply re-implement it here instead of re-using the code. Signed-off-by: AKASHI Takahiro <takahiro.akashi@linaro.org>
| * | efi_loader: Rename and correct values for ARM_SMC_MM_*Ilias Apalodimas2020-07-221-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Instead of adding the definition for the specific MM SVC used in StandAloneMM we added the one used in the standard SMC calls. So change the value from -4 to -5 to match the correct one defined in EDK2 and rename them to avoid future confusion Fixes 23a397d2e2fb: ("efi_loader: Add headers for EDK2 StandAloneMM communication") Signed-off-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | Merge tag 'u-boot-rockchip-20200722' of ↵Tom Rini2020-07-223-2/+25
|\ \ \ | |/ / |/| | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-rockchip - New rk3326 board: Hardkernel Odroid Go2; - Update board config and dts for RockPI 4/N8/N10; - Update led boot on support for roc-rk3399-pc; - Enable SPI Flash suppor for rk3328 rock64 board; - Update rockchip pcie phy to use generic framework;
| * | rockchip: evb_rk3288: Add console settingsSuniel Mahesh2020-07-221-1/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add console settings like stdin, stdout and stderr as usbkbd and vidconsole respectively for evb-rk3288 targets. This would certainly help to detect the attached video devices (like HDMI) and print the console messages on display. Signed-off-by: Suniel Mahesh <sunil@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: rk3399: Add default env to support compressed kernel ImageKever Yang2020-07-221-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add default kernel_comp_addr_r and kernel_comp_size to support boot from compressed kernel Image, this space is temporarily used during decompress according to README.distro. Reported-by: Tian Yuanhao <tianyuanhao@aliyun.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
| * | rockchip: board: add Hardkernel Odroid Go2 boardHeiko Stuebner2020-07-221-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | Also known as Odroid Go Advance but named Go2 internally by the vendor it seems. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* | | mtd: spinand: micron: identify SPI NAND device with Continuous Read modeShivamurthy Shastri2020-07-201-0/+1
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode. Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs. In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area. Hence, we disable the feature at probe time. Signed-off-by: Shivamurthy Shastri <sshivamurthy@micron.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
* | global_data: Add a generic global_data flag for SMP stateSimon Glass2020-07-201-0/+1
| | | | | | | | | | | | | | | | | | | | Allow keeping track of whether all CPUs have been enabled yet. This allows us to know whether other CPUs need to be considered when updating CPU-specific settings such as MTRRs on x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | mips: octeon: Add minimal Octeon 3 EBB7304 EVK supportStefan Roese2020-07-182-0/+39
|/ | | | | | | | | | | | | | | This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board. Supported devices: - UART - reset - CFI parallel NOR flash Signed-off-by: Stefan Roese <sr@denx.de>
* include: pci_ids: Add Cavium devicesSuneel Garapati2020-07-171-0/+18
| | | | | | | | | | Add VendorID and DeviceID for supported devices on OcteonTX/TX2 platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Reviewed-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* remove include/config_defaults.hRasmus Villemoes2020-07-173-24/+0
| | | | | | | | | | Since commit 4b0bcfa7c4ec (Kconfig: Migrate CONFIG_BOOTM_* options), the config_defaults.h file has been void of any actual content - and these days, "sane defaults for everyone" is achieved by appropriate default values in Kconfig. Remove it, and thus make every translation unit process one less header file. Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk>
* asm/u-boot.h: remove bd_t definitionsMasahiro Yamada2020-07-171-2/+2
| | | | | | | | All the users of bd_t were converted to struct bd_info. Remove the definitions. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
* treewide: convert bd_t to struct bd_info manuallyMasahiro Yamada2020-07-171-2/+2
| | | | | | | | | | | Some code was not converted by coccinelle, somehow. I manually fixed up the remaining, and comments, README docs. Signed-off-by: Masahiro Yamada <masahiroy@kernel.org> [trini: Add arch/arm/mach-davinci/include/mach/sdmmc_defs.h and include/fdt_support.h] Signed-off-by: Tom Rini <trini@konsulko.com>
* treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada2020-07-1713-69/+73
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux coding style guide (Documentation/process/coding-style.rst) clearly says: It's a **mistake** to use typedef for structures and pointers. Besides, using typedef for structures is annoying when you try to make headers self-contained. Let's say you have the following function declaration in a header: void foo(bd_t *bd); This is not self-contained since bd_t is not defined. To tell the compiler what 'bd_t' is, you need to include <asm/u-boot.h> #include <asm/u-boot.h> void foo(bd_t *bd); Then, the include direcective pulls in more bloat needlessly. If you use 'struct bd_info' instead, it is enough to put a forward declaration as follows: struct bd_info; void foo(struct bd_info *bd); Right, typedef'ing bd_t is a mistake. I used coccinelle to generate this commit. The semantic patch that makes this change is as follows: <smpl> @@ typedef bd_t; @@ -bd_t +struct bd_info </smpl> Signed-off-by: Masahiro Yamada <masahiroy@kernel.org>
* arm64: Remove CONFIG_SYS_FULL_VA macroMichal Simek2020-07-171-4/+0
| | | | | | | All configurations have been removed in 2016 by commit 7985cdf74b28 ("arm64: Remove non-full-va map code"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Convert CONFIG_ARMV7_PSCI_1_0 and CONFIG_ARMV7_PSCI_0_2 to KconfigPatrick Delaunay2020-07-175-9/+0
| | | | | | | | This converts the following to Kconfig: CONFIG_ARMV7_PSCI_1_0 CONFIG_ARMV7_PSCI_0_2 Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* common: bootm: add checks to verify if ramdisk / fdtimage overlaps OS imageTero Kristo2020-07-171-1/+2
| | | | | | | | These cases are typically fatal and are difficult to debug for random users. Add checks for detecting overlapping images and abort if overlap is detected. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* Convert CONFIG_MXC_UART to KconfigTom Rini2020-07-1754-58/+0
| | | | | | | | This converts the following to Kconfig: CONFIG_MXC_UART Signed-off-by: Tom Rini <trini@konsulko.com> Acked-by: Peng Fan <peng.fan@nxp.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-x86Tom Rini2020-07-1715-5/+1593
|\ | | | | | | | | | | | | | | | | | | - New timer API to allow delays with a 32-bit microsecond timer - Add dynamic ACPI structs (DSDT/SSDT) generations to the DM core - x86: Enable ACPI table generation by default - x86: Enable the copy framebuffer on Coral - x86: A few fixes to FSP2 with ApolloLake - x86: Drop setup_pcat_compatibility() - x86: Primary-to-Sideband Bus minor fixes
| * x86: irq: Support flags for acpi_gpeSimon Glass2020-07-171-0/+14
| | | | | | | | | | | | | | | | | | This binding currently has a flags cell but it is not used. Make use of it to create ACPI tables for interrupts. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * pmc: Move common registers to the header fileSimon Glass2020-07-171-0/+14
| | | | | | | | | | | | | | | | | | These registers need to be accesses from ACPI code, so move them to the header file. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * p2sb: Add a method to hide the busSimon Glass2020-07-171-1/+24
| | | | | | | | | | | | | | | | | | | | The P2SB bus needs to be hidden in some cases so that it does not get auto-configured by Linux. Add a method for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * x86: pinctrl: Add a way to get the pinctrl reg addressSimon Glass2020-07-171-0/+9
| | | | | | | | | | | | | | | | | | | | | | At present we can query the offset of a pinctrl register within the p2sb. For ACPI we need to get the actual address of the register. Add a function to handle this and rename the old one to more accurately reflect its purpose. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * acpi: Support writing named valuesSimon Glass2020-07-171-0/+72
| | | | | | | | | | | | | | | | | | | | Allow writing named integers and strings to the generated ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> [bmeng: Fix the "new blank line at EOF" warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * acpi: Support generation of a deviceSimon Glass2020-07-171-0/+9
| | | | | | | | | | | | | | | | | | | | Allow writing an ACPI device to the generated ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> [bmeng: Fix build failures on Sandbox] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * x86: Add bindings for NHLTSimon Glass2020-07-171-0/+24
| | | | | | | | | | | | | | | | | | Add devicetree bindings for the Intel Non-High-Definition-Audio Link Table (NHLT). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * acpi: Support generation of a generic registerSimon Glass2020-07-172-0/+29
| | | | | | | | | | | | | | | | | | | | Allow writing out a generic register. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> [bmeng: Fix build failures on Sandbox] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * acpi: Support generation of a scopeSimon Glass2020-07-171-0/+9
| | | | | | | | | | | | | | | | | | | | Add a function to write a scope to the generated ACPI code. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: Fix build failures on Sandbox] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * acpi: Export functions to write sized valuesSimon Glass2020-07-171-0/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | At present only acpigen_write_integer() is exported for use by other code. But in some cases it is useful to call the specific function depending on the size of the value. Export these functions and add a test. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: Fix the "new blank line at EOF" warning] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * dm: acpi: Add support for the NHLT tableSimon Glass2020-07-171-0/+26
| | | | | | | | | | | | | | | | | | | | | | | | The Intel Non-High-Definition-Audio Link Table (NHLT) table describes the audio codecs and connections in a system. Various devices can contribute information to produce the table. Add core support for this, based on a structure which is built up through calls to the driver. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
| * dm: core: Add a way of overriding the ACPI device pathSimon Glass2020-07-171-0/+13
| | | | | | | | | | | | | | | | | | Some devices such as GPIO need to override the normal path that would be generated by driver model. Add a device-tree property for this. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com>
generated by cgit (git 2.34.1) at 2024-11-19 02:46:55 +0000