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authorStefan Roese <sr@denx.de>2020-06-30 12:08:58 +0200
committerDaniel Schwierzeck <daniel.schwierzeck@gmail.com>2020-07-18 15:47:50 +0200
commit5fef24c912a44a08ab644aa16ceb5a435491f9d9 (patch)
tree786092a426377f81838509ada3d8c064bd58d8a6 /include
parente9609dc38ba225ddb58fcef41a0beb8a3b09a888 (diff)
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mips: octeon: Add minimal Octeon 3 EBB7304 EVK support
This patch adds very basic minimal support for the Marvell Octeon 3 CN73xx based EBB7304 EVK. Please note that the basic Octeon port does not support DDR3/4 initialization yet. To still use U-Boot on with this port, the L2 cache (4MiB) is used as RAM. This way, U-Boot can boot to the prompt on this board. Supported devices: - UART - reset - CFI parallel NOR flash Signed-off-by: Stefan Roese <sr@denx.de>
Diffstat (limited to 'include')
-rw-r--r--include/configs/octeon_common.h19
-rw-r--r--include/configs/octeon_ebb7304.h20
2 files changed, 39 insertions, 0 deletions
diff --git a/include/configs/octeon_common.h b/include/configs/octeon_common.h
new file mode 100644
index 0000000000..530f02ad3c
--- /dev/null
+++ b/include/configs/octeon_common.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-2020
+ * Marvell <www.marvell.com>
+ */
+
+#ifndef __OCTEON_COMMON_H__
+#define __OCTEON_COMMON_H__
+
+/* No DDR init yet -> run in L2 cache with limited resources */
+#define CONFIG_SYS_MALLOC_LEN (256 << 10)
+#define CONFIG_SYS_SDRAM_BASE 0xffffffff80000000
+#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
+
+#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + (1 << 20))
+
+#define CONFIG_SYS_INIT_SP_OFFSET 0x180000
+
+#endif /* __OCTEON_COMMON_H__ */
diff --git a/include/configs/octeon_ebb7304.h b/include/configs/octeon_ebb7304.h
new file mode 100644
index 0000000000..04fe4dfe22
--- /dev/null
+++ b/include/configs/octeon_ebb7304.h
@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright (C) 2019-2020
+ * Marvell <www.marvell.com>
+ */
+
+#ifndef __CONFIG_H__
+#define __CONFIG_H__
+
+#include "octeon_common.h"
+
+/*
+ * CFI flash
+ */
+#define CONFIG_SYS_MAX_FLASH_BANKS 1
+#define CONFIG_SYS_MAX_FLASH_SECT 256
+#define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_8BIT
+#define CONFIG_SYS_FLASH_EMPTY_INFO /* flinfo indicates empty blocks */
+
+#endif /* __CONFIG_H__ */