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* Merge tag 'u-boot-amlogic-20210514' of ↵Tom Rini2021-05-142-5/+21
|\ | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-amlogic - dts: add missing -u-boot.dtsi to enable HDMI on Beelink GTKing/King-Pro - usb: dwc3-meson-g12a: skip phy on -ENODATA aswell - net: dwmac_meson8b: do not set TX delay in TXID & RXID - net: designware: meson8b: add g12a compatible
| * net: designware: meson8b: add g12a compatibleNeil Armstrong2021-05-141-0/+1
| | | | | | | | | | | | Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
| * net: dwmac_meson8b: do not set TX delay in TXID & RXIDNeil Armstrong2021-05-141-4/+19
| | | | | | | | | | | | | | | | | | When the PHY interface is set as TXID & RXID, the delays should be taken from DT, but first they should not be hardcoded since the PHY driver will set them. Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| * usb: dwc3-meson-g12a: skip phy on -ENODATA aswellNeil Armstrong2021-05-141-1/+1
| | | | | | | | | | | | | | | | | | | | If the PHY isn't specified in the DT, -ENODATA means it should be skipped, handle it like -ENOENT. With that, devices without USB3 supported can have USB working (Odroid-HC4). Fixes: adb049abf7 ("usb: dwc3: Add Meson G12A USB Glue") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | pwm: sifive: make set_config() and set_enable() work properlyVincent Chen2021-05-141-10/+11
| | | | | | | | | | | | | | | | | | | | The pwm_sifive_set_config() and pwm_sifive_set_enable() cannot work properly due to the wrong implementations. It will cause the u-boot PWM command to not work as expected. The bugs will be resolved in this patch. Signed-off-by: Vincent Chen <vincent.chen@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
* | clk: Add support for the k210 clock driver pre-relocationSean Anderson2021-05-141-4/+10
| | | | | | | | | | | | | | | | Variables which had previously been stored in .bss are moved to .data. In addition, probed needs to be reset when the clock driver is re-bound post-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | clk: k210: Move the clint clock to under aclkSean Anderson2021-05-141-1/+1
| | | | | | | | | | | | | | No other (real) clocks have the cpu clock as their parent; instead they are children of aclk. Move the clint clock under aclk to match them. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | clk: k210: Remove k210_register_pllSean Anderson2021-05-142-28/+3
| | | | | | | | | | | | | | This simplifies the PLL creation process, since we don't have to pass all the parameters individually. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | clk: k210: Fix PLL enable always getting takenSean Anderson2021-05-141-1/+2
| | | | | | | | | | | | | | | | | | This conditional always evaluated as false, regardless of the value of reg. Fix it so that it properly tests the bits in the PLL register. Also test PLL_EN, now that we set it. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
* | clk: k210: Fix PLLs not being enabledSean Anderson2021-05-141-0/+2
| | | | | | | | | | | | | | | | | | | | After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
* | clk: Warn on failure to assign rateSean Anderson2021-05-141-4/+7
|/ | | | | | | | If the user/dev explicitly requests a clock be assigned a certain rate, then we should warn them if we can't do it. This makes it clear if the clock is running at the default rate. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* w1: replace dt detection by automatic detectionKory Maincent2021-05-134-33/+87
| | | | | | | | | | | | This patch changes the functioning of the detection of w1 devices. The old way was a comparison between detected w1 and the ones described in the device tree. Now it will just look for the driver matching the family id of the w1 detected. The patch is inspired from Maxime Ripard code. Signed-off-by: Kory Maincent <kory.maincent@bootlin.com> Reviewed-by: Maxime Ripard <maxime@cerno.tech>
* Merge tag 'ti-v2021.07-rc3' of ↵Tom Rini2021-05-1283-23478/+47964
|\ | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-ti - Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
| * net: ti: am65-cpsw-nuss: Add a new compatible for AM64Vignesh Raghavendra2021-05-121-0/+1
| | | | | | | | | | | | Add a new compatible to support AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * net: ti: am65-cpsw-nuss: Don't cache disabled port IDVignesh Raghavendra2021-05-121-1/+1
| | | | | | | | | | | | | | | | Currently driver may end up caching disabled port ID as active interface. Fix this by bailing out earlier in case port is marked disabled in the DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * net: ti: am65-cpsw-nuss: Prepare to support non primary ext portVignesh Raghavendra2021-05-121-1/+1
| | | | | | | | | | | | | | | | | | CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8) Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port) as preparation to allow any one of the 8 ports to be used as ethernet interface in U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * dma: ti: k3-udma: Add BCDMA and PKTDMA supportVignesh Raghavendra2021-05-121-64/+939
| | | | | | | | | | | | Sync BCDMA and PKTDMA support from Kernel for AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * dma: ti: k3-psil-am64: Add AM64 PSIL endpoint dataVignesh Raghavendra2021-05-124-0/+160
| | | | | | | | | | | | Add AM64 SoC specific channel mapping and endpoint data. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * dma: ti: k3-psil: Extend PSIL EP data extension for AM64Vignesh Raghavendra2021-05-121-0/+16
| | | | | | | | | | | | Extend PSIL EP data to include AM64 DMA specific information Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * dma: ti: k3-psil-am654: Drop unused PSIL EP static dataVignesh Raghavendra2021-05-121-25/+7
| | | | | | | | | | | | | | | | | | | | ICSSG Ethernet driver uses two src threads per port (one per slice). Similarly CPSW uses one src thread. Drop PSIL EP static data for other src threads in order to reduce R5 SPL footprint. This makes AM65x board bootable again. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * soc: ti: k3-navss-ringacc: Remove unused ring modesVignesh Raghavendra2021-05-121-304/+7
| | | | | | | | | | | | | | | | | | | | | | | | With AM64x supporting only K3_NAV_RINGACC_RING_MODE_RING or the exposed ring mode, all other K3 SoCs have also been moved to this common baseline. Therefore drop other modes such as K3_NAV_RINGACC_RING_MODE_MESSAGE (and proxy) to save on SPL footprint. There is a saving of ~800 bytes with this change for am65x_evm_r5_defconfig. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
| * soc: ti: k3-navss-ringacc: Add AM64 ringacc supportVignesh Raghavendra2021-05-121-5/+268
| | | | | | | | | | | | | | | | | | | | | | | | AM64 dual mode rings are modeled as pair of Rings objects which has common configuration and memory buffer, but separate real-time control register sets for each direction mem2dev (forward) and dev2mem (reverse). AM64 rings must be requested only using k3_ringacc_request_rings_pair(), and forward ring must always be initialized/configured. After this any other Ringacc APIs can be used without any callers changes. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * firmware: ti_sci: Update ti_sci_cmd_rm_udmap_tx_ch_cfg() API to the latestVignesh Raghavendra2021-05-122-0/+21
| | | | | | | | | | | | | | Update struct ti_sci_msg_rm_udmap_tx_ch_cfg_req to latest ABI to support AM64x BCDMA Block copy channels. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * soc: ti: k3-socinfo: Add entry for AM64X SoC familyLokesh Vutla2021-05-121-0/+4
| | | | | | | | | | | | Add support for AM64 SoC identification. Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
| * ram: k3-ddrss: Enable vtt regulator if presentLokesh Vutla2021-05-121-0/+14
| | | | | | | | | | | | | | | | | | Attempt to get and enable a vtt regulator if one is provided from the dts. If we do not find one, continue as not all platforms have this. Signed-off-by: Nishanth Menon <nm@ti.com> Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-ddrss: Introduce support for AM642 SoCsDave Gerlach2021-05-1220-0/+23490
| | | | | | | | | | | | | | | | | | | | | | | | | | Introduce support for the AM64 DDRSS controller which uses the 16bit variation of the controller. This controller shares much functionality with the existing J721e support, so this patch introduces only the new code needed for am64 specific support from "_16bit_" files with headers under "16bit/" include path/. Also add a CONFIG_K3_AM64_DDRSS option to the choice required for use with CONFIG_K3_DDRSS to allow selecting AM64 support. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-ddrss: Introduce common driver with J7 SoC supportDave Gerlach2021-05-1227-3849/+3675
| | | | | | | | | | | | | | | | | | Introduce a new version of the ddr driver which has the ability to support different variations of the controller. Also introduce support for the 32bit variation of the controller which is what was already supported by the previous version used for J721e and J7200. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-ddrss: Introduce top-level CONFIG_K3_DDRSSDave Gerlach2021-05-122-2/+11
| | | | | | | | | | | | | | | | | | Create a new CONFIG_K3_DDRSS option to select the common parts of the k3-ddrss driver. Also introduce a choice that depends on the top level option to select CONFIG_K3_J721E_DDRSS for j721e support, and update corresponding Kconfig as required. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: Rename to k3-ddrssDave Gerlach2021-05-1220-1/+1
| | | | | | | | | | | | | | | | Rename the k3-j721e folder under drivers/ram to k3-ddrss in preparation of introducing additional support for other platforms to the same driver. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: lpddr4_ctl_regs: Fix checkpatch issue for typesDave Gerlach2021-05-121-1514/+1514
| | | | | | | | | | | | Use Linux style u32 instead of uint32_t. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: lpddr4_pi_macros: Fix indentation issuesDave Gerlach2021-05-121-2801/+2801
| | | | | | | | | | | | | | | | Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: lpddr4_phy_core_macros: Fix indentation issuesDave Gerlach2021-05-121-694/+694
| | | | | | | | | | | | | | | | Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: lpddr4_ddr_controller_macros: Fix indentation issuesDave Gerlach2021-05-121-3681/+3681
| | | | | | | | | | | | | | | | Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: lpddr4_data_slice_3_macros: Fix indentation issuesDave Gerlach2021-05-121-677/+677
| | | | | | | | | | | | | | | | Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: lpddr4_data_slice_2_macros: Fix indentation issuesDave Gerlach2021-05-121-677/+677
| | | | | | | | | | | | | | | | Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: lpddr4_data_slice_1_macros: Fix indentation issuesDave Gerlach2021-05-121-677/+677
| | | | | | | | | | | | | | | | Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: lpddr4_data_slice_0_macros: Fix indentation issuesDave Gerlach2021-05-121-717/+717
| | | | | | | | | | | | | | | | Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * ram: k3-j721e: lpddr4_address_slice_0_macros: Fix indentation issuesDave Gerlach2021-05-121-167/+167
| | | | | | | | | | | | | | | | Fix the indentation for certain macros to be consistent with the other macros in the file, as the existing indentation does not make sense in many places. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * mailbox: k3-sec-proxy: Extend valid thread IDsDave Gerlach2021-05-121-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | AM64x uses a different thread mapping that existing K3 SoCs, so update the valid thread ID list to include those used for AM64x. Also remove the comment identifying the purpose of each thread ID. The purpose of the thread ID is specified when describing the threads in the device tree and the same ID can mean different things on different SoCs, so the comment is not useful. Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * mmc: sdhci_am654: Add Support for TI's AM642 SoCDave Gerlach2021-05-121-0/+18
| | | | | | | | | | | | | | | | | | | | Add support for the controller present on the AM642 SoC. There are instances: sdhci0: 8bit bus width, max 400 MBps sdhci1: 4bit bus width, max 100 MBps Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
| * Revert "fdt: translate address if #size-cells = <0>"Dario Binacchi2021-05-125-24/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit d64b9cdcd475eb7f07b49741ded87e24dae4a5fc. As pointed by [1] and [2], the reverted patch made every DT 'reg' property translatable. What the patch was trying to fix was fixed in a different way from previously submitted patches which instead of correcting the generic address translation function fixed the issue with appropriate platform code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
| * clk: ti: am3-dpll: use custom API for memory accessDario Binacchi2021-05-121-33/+53
| | | | | | | | | | | | | | | | | | | | Using the custom TI functions required not only replacing common memory access functions but also rewriting the routines used to set bypass and lock states. As for readl() and writel(), they also required the address of the register to be accessed, a parameter that is hidden by the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: gate: use custom API for memory accessDario Binacchi2021-05-121-11/+12
| | | | | | | | | | | | | | Replaces the common memory access functions used by the driver with the ones exported from the TI clk module. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: change clk_ti_latch() signatureDario Binacchi2021-05-124-24/+28
| | | | | | | | | | | | | | | | | | The clock access functions exported by the clk header use the struct clk_ti_reg parameter to get the address of the register. This must also apply to clk_ti_latch(). Changes to TI's clk-mux and clk-divider drivers prevented the patch from generating compile errors. Signed-off-by: Dario Binacchi <dariobin@libero.it>
| * clk: ti: add custom API for memory accessDario Binacchi2021-05-122-0/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As pointed by [1] and [2], commit d64b9cdcd4 ("fdt: translate address if #size-cells = <0>") is wrong: - It makes every 'reg' DT property translatable. It changes the address translation so that for an I2C 'reg' address you'll get back as reg the I2C controller address + reg value. - The quirk must be fixed with platform code. The clk_ti_get_reg_addr() is the platform code able to make the correct address translation for the AM33xx clocks registers. Its implementation was inspired by the Linux Kernel code. [1] https://patchwork.ozlabs.org/project/uboot/patch/1614324949-61314-1-git-send-email-bmeng.cn@gmail.com/ [2] https://lore.kernel.org/linux-clk/20210402192054.7934-1-dariobin@libero.it/T/ Signed-off-by: Dario Binacchi <dariobin@libero.it>
* | Merge tag 'u-boot-imx-20210502' of ↵Tom Rini2021-05-113-9/+25
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210502 ------------------- - mx6: fixes for Ventana - local fixes from maintainer - imx7d: Ronetix's iMX7-CM - imx8: Ronetix iMX8MQ-CM Engicam i.Core MX8M Compulab iot-gate-imx8 - Fixes i.MX8 documentation - Fixes phy usage with fec
| * | pci: imx: disable imx6sdl LTSSM upon driver removeTim Harvey2021-05-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 6ecbe1375671 ("drivers: pci: imx: add imx_pcie_remove function") attempted to resolve an issue caused by MX6QDL not having a proper intneral PCIe core reset and thus hanging during kernel init if the bootloader had enabled PCI. The issue exists for IMX6Q, IMX6D, IXM6S, and IMX6DL. Fix the case for IMX6S and IMX6DL getting missed. This fixes IMX6S and IMX6DL with PCI enabled in U-Boot booting for Linux v4.11+. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
| * | net: fec: Only unregister MII bus if we registered itSean Anderson2021-05-021-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If we fail to probe for whatever reason, we cannot unregister/free the MII bus unless we registered it with fec_get_miibus. This fixes FECs sharing an MDIO bus from destroying it, preventing the other FEC from using it. Fixes: 6a895d039b ("net: Update eQos driver and FEC driver to use eth phy interfaces") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| * | net: fec: Don't use disabled physSean Anderson2021-05-021-6/+9
| | | | | | | | | | | | | | | | | | | | | If a phy is disabled, don't use it. This matches Linux's behavior. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| * | pci: pci-uclass: Add board_pci_fixup_dev for DM_PCITim Harvey2021-05-021-0/+6
| | | | | | | | | | | | | | | | | | | | | Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
generated by cgit (git 2.34.1) at 2024-06-24 00:57:29 +0000