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| * | imx: ddr: imx8m: Move selfref_en after DDR scrubYe Li2021-01-231-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When doing DDR scrub, the DDR may enter into self refresh if the selfref_en is enabled before DDR scrub. This will cause scrub can't complete that SBRSTAT.scrub_done won't be set. Since the selfref_en can be programmed during the course of normal operation, move it after DDR scrub Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* | | Merge tag 'u-boot-atmel-2021.04-b' of ↵Tom Rini2021-01-253-18/+161
|\ \ \ | |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.04 cycle This feature set includes macb updates for all interfaces and new sama7g5 variant support; micrel ksz9031 DLL support; a new board from Giant based on Adafruit feather form factor which contains a SAMA5D27 SoC; several fixes regarding the NAND flash PMECC block; and pincontrol drive strength support for pio4 controller.
| * | net: macb: take into account all RGMII interface typesClaudiu Beznea2021-01-221-1/+4
| | | | | | | | | | | | | | | | | | | | | Take into account all RGMII interface types. Depending on it the RGMII PHY's timings are setup. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | net: macb: add support for sama7g5 emacClaudiu Beznea2021-01-221-0/+9
| | | | | | | | | | | | | | | | | | Add support for SAMA7G5 EMAC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | net: macb: add support for sama7g5 gmacClaudiu Beznea2021-01-221-0/+33
| | | | | | | | | | | | | | | | | | Add support for SAMA7G5 GMAC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | net: macb: check clk_set_rate return value to be negativeClaudiu Beznea2021-01-221-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | clk_set_rate() returns the set rate in case of success and a negative number in case of failure. Consider failure only the negative numbers. Fixes: 3ef64444de157 ("dm: net: macb: Implement link speed change callback") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | net: macb: add user io config data structureClaudiu Beznea2021-01-221-12/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Different implementation of USER IO register needs different mapping for bit fields of this register. Add implementation for this and, since clken is part of USER IO and it needs to be activated based on per SoC capabilities, add caps in macb_config where clken specific information needs to be filled. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | pinctrl: at91-pio4: implement drive strength supportEugen Hristev2021-01-221-0/+8
| | | | | | | | | | | | | | | | | | | | | Implement drive strength support, by preserving the same bindings as in Linux. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | pinctrl: at91-pio4: convert to dev_read_propEugen Hristev2021-01-221-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Use dev_read_prop instead of using the fdt_read_property which reads from the GD struct's fdt. This way the node is accessed via the device config instead of the global struct, which makes code more portable and GD independent. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
| * | net: phy: micrel: fix typoClaudiu Beznea2021-01-191-1/+1
| | | | | | | | | | | | | | | | | | Fix typo. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * | net: phy: micrel: add support for DLL setup on ksz9131Claudiu Beznea2021-01-191-1/+62
| | | | | | | | | | | | | | | | | | Add support for DLL setup on KSZ9131. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-samsung.gitTom Rini2021-01-221-56/+0
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| * | mmc: exynos_dw_mmc: remove unused functionJaehoon Chung2021-01-131-56/+0
| | | | | | | | | | | | | | | | | | | | | | | | Remove unused function in exynos_dw_mmc.c. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | | pci: Add Rockchip dwc based PCIe controller driverShawn Lin2021-01-214-0/+890
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add Rockchip dwc based PCIe controller driver for rk356x platform. Driver support Gen3 by operating as a Root complex. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | | phy: rockchip: Add Rockchip Synopsys PCIe 3.0 PHYShawn Lin2021-01-213-0/+164
| | | | | | | | | | | | | | | | | | | | | | | | | | | Add the Rockchip Synopsys based PCIe 3.0 PHY driver as part of Generic PHY framework. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* | | mmc: xenon_sdhci: Remove duplicated macrosMichal Simek2021-01-201-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | There is no need to define the same macros in drivers. All macros have been added by commit 17a42abb40dd ("mmc: Define timing macro's"). Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | net: dwc_eth_qos: Pad descriptors to cacheline sizeMarek Vasut2021-01-191-78/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words after the descriptor. Use this to pad the descriptors to cacheline size and remove the need for noncached memory altogether. Moreover, this lets Tegra use the generic cache flush / invalidate operations. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | | net: ks8851: Reset internal RXFC count on bad packetMarek Vasut2021-01-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A sporadic condition occurs when the "bad packet" error is triggered repeatedly, which results in "bad packet" messages scrolling on the console during transfer. To avoid triggering this, reset the internal RXFC count on the first occurance of the "bad packet", which forces the code to re-read the RX packet count from the MAC, and prevents any additional "bad packet" messages if there are no more packets in the MAC. Also print better debug information if this condition occurs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Tom Rini <trini@konsulko.com>
* | | net: ftgmac100: Read and retain MAC addressHongwei Zhang2021-01-191-0/+32
| | | | | | | | | | | | | | | | | | Read and retain MAC address across flash and QEMU support. Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
* | | net: e1000: implement eth_write_hwaddr for DM_ETHIan Ray2021-01-191-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | Implement programming MAC address to the hardware also for device model configuration. Fixes: b565b18a294f ("board: ge: bx50v3: Enable DM for PCI and ethernet") Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
* | | timer: mtk_timer: initialize the timer before useWeijie Gao2021-01-181-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The timer being used by this driver may have already been used by first stage bootloader (e.g. ATF/preloader), and it's settings may differ from what this driver is going to use. This may cause issues, such as inaccurate timer frequency due to incorrect clock divider. This patch adds the initialization code to avoid them. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* | | pinctrl: mediatek: correct error handlingHeinrich Schuchardt2021-01-181-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If no GPIO controller is found, the return value should not depend on a random value on the stack. Initialize variable ret. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Acked-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
* | | mtd: remove drivers/mtd/mw_eeprom.cHeinrich Schuchardt2021-01-182-239/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | drivers/mtd/mw_eeprom.c contains code that never worked. mw_eeprom_write() and mw_eeprom_read() have incorrect loop conditions: while (len <= 2) { CONFIG_MW_EEPROM is not set anywhere. So let's simply drop the module. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | drivers: qe: avoid double free()Heinrich Schuchardt2021-01-181-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | Avoid calling free(addr) twice if the device for ucode is not found. The problem was indicated by cppcheck. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | mmc: fsl_esdhc_spl: remove superfluous free()Heinrich Schuchardt2021-01-181-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | Freeing a buffer before calling hang() is superfluous. Removing the call reduces the SPL size. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | dma: bcm6348: incorrect buffer allocationHeinrich Schuchardt2021-01-181-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calling calloc() for 0 members does not make any sense. Setting ch_priv->busy_desc = NULL for ch_priv->desc_cnt > 0 is equally unreasonable. The current code will lead to a NULL dereference in bcm6348_iudma_enable(). The assignments for ch_priv->busy_desc are obviously swapped. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | | power: pmic: add driver for Monolithic Power mp5416Tim Harvey2021-01-183-0/+114
| | | | | | | | | | | | | | | | | | | | | | | | This adds basic register access and child regulator binding for the Monolithic MP5416 Power Management IC which integrates four DC/DC switching converters and five LDO regulators. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* | | aspeed: Add AST2600 platform supportChia-Wei, Wang2021-01-181-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add low level platform initialization for the AST2600 SoC. The 2-stage booting with U-Boot SPL are leveraged to support different booting mode. However, currently the patch supports only the booting from memory-mapped SPI flash. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | reset: aspeed: Add AST2600 reset supportChia-Wei, Wang2021-01-183-0/+118
| | | | | | | | | | | | | | | | | | | | | | | | Add controller reset support through the System Control Unit (SCU) of AST2600 SoC. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | wdt: aspeed: Add AST2600 watchdog supportChia-Wei, Wang2021-01-183-0/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AST2600 has 8 watchdog timers including 8 sets of 32-bit decrement counters, based on 1MHz clock. A 64-bit reset mask is also supported to specify which controllers should be reset by the WDT reset. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | ram: aspeed: Add AST2600 DRAM control supportDylan Hung2021-01-183-2/+1123
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AST2600 supports DDR4 SDRAM with maximum speed DDR4-1600. The DDR4 DRAM types including 128MbX16 (2Gb), 256MbX16 (4Gb), 512MbX16 (8Gb), 1GbX16 (16Gb), and 1GbX8 TwinDie (16Gb) are supported. Signed-off-by: Dylan Hung <dylan_hung@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
* | | clk: aspeed: Add AST2600 clock supportRyan Chen2021-01-182-0/+1174
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds the clock control driver for the AST2600 SoC. Signed-off-by: Ryan Chen <ryan_chen@aspeedtech.com> Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com>
* | | mtd: rawnand: cortina_nand: Add Cortina CAxxxx SoC supportKate Liu2021-01-184-0/+1696
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add Cortina Access parallel Nand support for CAxxxx SOCs Signed-off-by: Kate Liu <kate.liu@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Tom Rini <trini@konsulko.com> CC: Scott Wood <oss@buserror.net> Reviewed-by: Tom Rini <trini@konsulko.com>
* | | mmc: Only retrieve cd pin when GPIO is enabledHarm Berntsen2021-01-181-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | The driver only needs to retrieve the pin for the ACPI info. The driver itself works without depending on GPIO. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | clk: mediatek: Add MT8183 clock driverFabien Parent2021-01-182-0/+824
| |/ |/| | | | | | | | | | | Add the topckgen, apmixedsys and infracfg clock driver for the MT8183 SoC. Signed-off-by: Fabien Parent <fparent@baylibre.com>
* | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-shTom Rini2021-01-181-5/+72
|\ \ | | | | | | | | | - R-Car pinctrl updates
| * | pinctrl: renesas: Implement get_pin_muxing() callbackLad Prabhakar2021-01-181-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | Implement get_pin_muxing() callback so that pinmux status command can be used on Renesas platforms. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
| * | pinctrl: renesas: Make sure the pin type is updated after setting the MUXLad Prabhakar2021-01-181-5/+47
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | By default on startup all the pin types are configured to PINMUX_TYPE_NONE (in sh_pfc_map_pins()), when pin is set as GPIO the pin type is updated to PINMUX_TYPE_GPIO. But the type is not updated when the pin is set as a function in sh_pfc_pinctrl_pin_set() or sh_pfc_pinctrl_group_set() calls (these calls only set the MUX if the pin type is PINMUX_TYPE_NONE ie unused). So with the current implementation pin functionality could be overwritten silently, for example if the same pin is added for SPI and serial. This patch makes sure of updating pin type after every successful call to sh_pfc_config_mux() and thus fixing from pin functionality to be overwritten. Also a warning message is printed if the current pin is being overwritten before abort. This also avoids pin re-muxing to same type that is for example from command line device is asked to re-probe/select (mmc dev x) we return early with success in this case as the pin is already muxed. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-riscvTom Rini2021-01-1813-20/+707
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Update qemu-riscv.rst build instructions. - Add support for SPI on Kendryte K210. - Add Microchip PolarFire SoC Icicle Kit support. - Add support for an early timer. - Select TIMER_EARLY to avoid infinite recursion for Trace.
| * | | clk: Add Microchip PolarFire SoC clock driverPadmarao Begari2021-01-188-0/+514
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add clock driver code for the Microchip PolarFire SoC. This driver handles reset and clock control of the Microchip PolarFire SoC device. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * | | net: macb: Add phy address to read it from device treePadmarao Begari2021-01-181-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Read phy address from device tree and use it to find the phy device if not found then search in the range of 0 to 31. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * | | net: macb: Add DMA 64-bit address support for macbPadmarao Begari2021-01-182-17/+120
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable 32-bit or 64-bit DMA in the macb driver based on the macb hardware compatibility and it is configured with structure macb_config in the driver. The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
| * | | riscv: timer: Add support for an early timerPragnesh Patel2021-01-183-3/+60
| |/ / | | | | | | | | | | | | | | | | | | | | | Added support for timer_early_get_count() and timer_early_get_rate() This is mostly useful in tracing. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Rick Chen <rick@andestech.com>
* | | ram: k3-j721e: rename BIT_MASK()Heinrich Schuchardt2021-01-162-15/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The macro BIT_MASK is already defined in include/linux/bitops.h. To avoid name collisions rename BIT_MASK() in drivers/ram/k3-j721e/lpddr4_private.h to LPDDR4_BIT_MASK(). Remove superfluous parantheses. Remove superfluous comparison to 0. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | mtd: misplaced log.h and dm/devres.hHeinrich Schuchardt2021-01-161-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | log.h and dm/devres.h are U-Boot includes. So placing them behind #ifndef __UBOOT__ does not make any sense. Fixes: f7ae49fc4f36 ("common: Drop log.h from common header") Fixes: 61b29b826838 ("dm: core: Require users of devres to include the header") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* | | drivers: serial: probe all uart devicesVabhav Sharma2021-01-162-0/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot DM model probe only single device at a time which is enabled and configured using device tree or platform data method. PL011 UART IP is SBSA compliant and firmware does the serial port set-up, initialization and let the kernel use UART port for sending and receiving characters. Normally software talk to one serial port time but some LayerScape platform require all the UART devices enabled in Linux for various use case. Adding support to probe all enabled serial devices like SBSA compliant PL011 UART ports probe and initialization by firmware. Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* | | dm: core: add function uclass_probe_all() to probe all devicesVabhav Sharma2021-01-161-0/+19
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support a common method to probe all devices associated with uclass. This includes data structures and code for finding the first device and looping for remaining devices associated with uclasses (groups of devices with the same purpose, e.g. all SERIAL ports will be in the same uclass). An example is SBSA compliant PL011 UART IP, where firmware does the serial port initialization and prepare uart device to let the kernel use it for sending and reveiving the characters.SERIAL uclass will use this function to initialize PL011 UART ports. The feature is enabled with CONFIG_DM. Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* | | power: regulator: Kconfig: add a dependency for POWER_SUPPORT for SPLNishanth Menon2021-01-161-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | power/regulator will not be built if just CONFIG_SPL_DM_REGULATOR is enabled. It needs CONFIG_SPL_POWER_SUPPORT to be enabled as well. For example, if we just need a GPIO regulator in SPL: CONFIG_DM_REGULATOR=y CONFIG_SPL_DM_REGULATOR=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_SPL_DM_REGULATOR_GPIO=y Will not suffice, since the entire regulator build for SPL depends on CONFIG_SPL_POWER_SUPPORT. Elaborate that information in the Kconfig dependency. Signed-off-by: Nishanth Menon <nm@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | Kconfig: simple panel requires backlightMarcin Juszkiewicz2021-01-161-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | During build of simple panel driver backlight is needed so let's enable it: aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_set_backlight': u-boot/drivers/video/simple_panel.c:43: undefined reference to `backlight_set_brightness' aarch64-linux-gnu-ld.bfd: drivers/built-in.o: in function `simple_panel_enable_backlight': u-boot/drivers/video/simple_panel.c:28: undefined reference to `backlight_enable' Signed-off-by: Marcin Juszkiewicz <marcin@juszkiewicz.com.pl>
* | disk: dos: rename write_mbr_partition to write_mbr_sectorMarek Szyprowski2021-01-151-1/+1
| | | | | | | | | | | | | | | | write_mbr_partition() function name is a bit misleading, so rename it to write_mbr_sector(). This is a preparation for adding code for writing a complete MBR partition layout. Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
generated by cgit (git 2.34.1) at 2024-07-02 01:00:30 +0000