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authorChia-Wei, Wang <chiawei_wang@aspeedtech.com>2020-12-14 13:54:25 +0800
committerTom Rini <trini@konsulko.com>2021-01-18 15:23:05 -0500
commit337d95c4aa200979181c06ca53e3b45b77655ecf (patch)
tree965985c3b84900b51d6db8aeb4814a1218704a6a /drivers
parentfde93143469fbf1ee6fdd3471d72f27dce6ecc5c (diff)
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wdt: aspeed: Add AST2600 watchdog support
AST2600 has 8 watchdog timers including 8 sets of 32-bit decrement counters, based on 1MHz clock. A 64-bit reset mask is also supported to specify which controllers should be reset by the WDT reset. Signed-off-by: Chia-Wei, Wang <chiawei_wang@aspeedtech.com> Reviewed-by: Ryan Chen <ryan_chen@aspeedtech.com>
Diffstat (limited to 'drivers')
-rw-r--r--drivers/watchdog/Kconfig9
-rw-r--r--drivers/watchdog/Makefile1
-rw-r--r--drivers/watchdog/ast2600_wdt.c110
3 files changed, 120 insertions, 0 deletions
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
index 4532a40e45..d5edabf3ef 100644
--- a/drivers/watchdog/Kconfig
+++ b/drivers/watchdog/Kconfig
@@ -86,6 +86,15 @@ config WDT_ASPEED
It currently does not support Boot Flash Addressing Mode Detection or
Second Boot.
+config WDT_AST2600
+ bool "Aspeed AST2600 watchdog timer support"
+ depends on WDT
+ default y if ASPEED_AST2600
+ help
+ Select this to enable watchdog timer for Aspeed ast2500/ast2400 devices.
+ The watchdog timer is stopped when initialized. It performs reset, either
+ full SoC reset or CPU or just some peripherals, based on the flags.
+
config WDT_AT91
bool "AT91 watchdog timer support"
depends on WDT
diff --git a/drivers/watchdog/Makefile b/drivers/watchdog/Makefile
index 01b8231f2b..cbb6d8407c 100644
--- a/drivers/watchdog/Makefile
+++ b/drivers/watchdog/Makefile
@@ -19,6 +19,7 @@ obj-$(CONFIG_$(SPL_TPL_)WDT) += wdt-uclass.o
obj-$(CONFIG_WDT_SANDBOX) += sandbox_wdt.o
obj-$(CONFIG_WDT_ARMADA_37XX) += armada-37xx-wdt.o
obj-$(CONFIG_WDT_ASPEED) += ast_wdt.o
+obj-$(CONFIG_WDT_AST2600) += ast2600_wdt.o
obj-$(CONFIG_WDT_BCM6345) += bcm6345_wdt.o
obj-$(CONFIG_WDT_CORTINA) += cortina_wdt.o
obj-$(CONFIG_WDT_ORION) += orion_wdt.o
diff --git a/drivers/watchdog/ast2600_wdt.c b/drivers/watchdog/ast2600_wdt.c
new file mode 100644
index 0000000000..bc9842089b
--- /dev/null
+++ b/drivers/watchdog/ast2600_wdt.c
@@ -0,0 +1,110 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (c) 2020 Aspeed Technology, Inc
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <errno.h>
+#include <log.h>
+#include <wdt.h>
+#include <asm/io.h>
+#include <asm/arch/wdt_ast2600.h>
+#include <linux/err.h>
+
+struct ast2600_wdt_priv {
+ struct ast2600_wdt *regs;
+};
+
+static int ast2600_wdt_start(struct udevice *dev, u64 timeout_ms, ulong flags)
+{
+ struct ast2600_wdt_priv *priv = dev_get_priv(dev);
+ struct ast2600_wdt *wdt = priv->regs;
+
+ /* WDT counts in the 1MHz frequency, namely 1us */
+ writel((u32)(timeout_ms * 1000), &wdt->counter_reload_val);
+ writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart);
+ writel(WDT_CTRL_EN | WDT_CTRL_RESET, &wdt->ctrl);
+
+ return 0;
+}
+
+static int ast2600_wdt_stop(struct udevice *dev)
+{
+ struct ast2600_wdt_priv *priv = dev_get_priv(dev);
+ struct ast2600_wdt *wdt = priv->regs;
+
+ clrbits_le32(&wdt->ctrl, WDT_CTRL_EN);
+
+ writel(WDT_RESET_MASK1_DEFAULT, &wdt->reset_mask1);
+ writel(WDT_RESET_MASK2_DEFAULT, &wdt->reset_mask2);
+
+ return 0;
+}
+
+static int ast2600_wdt_reset(struct udevice *dev)
+{
+ struct ast2600_wdt_priv *priv = dev_get_priv(dev);
+ struct ast2600_wdt *wdt = priv->regs;
+
+ writel(WDT_COUNTER_RESTART_VAL, &wdt->counter_restart);
+
+ return 0;
+}
+
+static int ast2600_wdt_expire_now(struct udevice *dev, ulong flags)
+{
+ int ret;
+ struct ast2600_wdt_priv *priv = dev_get_priv(dev);
+ struct ast2600_wdt *wdt = priv->regs;
+
+ ret = ast2600_wdt_start(dev, 1, flags);
+ if (ret)
+ return ret;
+
+ while (readl(&wdt->ctrl) & WDT_CTRL_EN)
+ ;
+
+ return ast2600_wdt_stop(dev);
+}
+
+static int ast2600_wdt_of_to_plat(struct udevice *dev)
+{
+ struct ast2600_wdt_priv *priv = dev_get_priv(dev);
+
+ priv->regs = dev_read_addr_ptr(dev);
+ if (!priv->regs)
+ return -EINVAL;
+
+ return 0;
+}
+
+static const struct wdt_ops ast2600_wdt_ops = {
+ .start = ast2600_wdt_start,
+ .reset = ast2600_wdt_reset,
+ .stop = ast2600_wdt_stop,
+ .expire_now = ast2600_wdt_expire_now,
+};
+
+static const struct udevice_id ast2600_wdt_ids[] = {
+ { .compatible = "aspeed,ast2600-wdt" },
+ { }
+};
+
+static int ast2600_wdt_probe(struct udevice *dev)
+{
+ debug("%s() wdt%u\n", __func__, dev_seq(dev));
+ ast2600_wdt_stop(dev);
+
+ return 0;
+}
+
+U_BOOT_DRIVER(ast2600_wdt) = {
+ .name = "ast2600_wdt",
+ .id = UCLASS_WDT,
+ .of_match = ast2600_wdt_ids,
+ .probe = ast2600_wdt_probe,
+ .priv_auto = sizeof(struct ast2600_wdt_priv),
+ .of_to_plat = ast2600_wdt_of_to_plat,
+ .ops = &ast2600_wdt_ops,
+};