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* dm: core: Skip adding uclasses with OF_PLATDATA_INSTSimon Glass2021-03-221-1/+4
| | | | | | | | There is no need to ever add new uclasses since these are set up at build time. Update the code to return an error if this is attempted. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Set up driver model for OF_PLATDATA_INSTSimon Glass2021-03-221-12/+30
| | | | | | | | | | | With this we don't need to scan and bind drivers, not even the root device. We just need to locate the root device that was set up at build time, then set our root in global_data to point to it. Update the code to handle this case. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Adjust uclass setup with of-platdataSimon Glass2021-03-221-2/+6
| | | | | | | | | When OF_PLATDATA_INST is enabled we don't need to create the uclass list. Instead we just need to point to the existing list. Update the code accordingly. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Allow dropping run-time binding of devicesSimon Glass2021-03-221-17/+25
| | | | | | | | | | | | With OF_PLATDATA_INST devices are bound at build time. We should not need binding of devices at runtime in most cases. However it is inflexible to absolutely prohibit it, so add an option to control this. Update the driver model core so that it does not bind devices. Update device_bind() to return an error if called. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* bus: ti-sysc: change in a normal driverDario Binacchi2021-03-221-6/+0
| | | | | | | | | | | | | | The module defines a duplicate uclass driver for UCLASS_SIMPLE_BUS, but it is not allowed. This breaks of-platdata and makes the result non-deterministic. The driver does not need to be an uclass driver, so lets remove it. I had turned it into an uclass driver because I thought wrongly it had to call the dm_scan_fdt_dev routine to work properly, but some tests on the board have shown otherwise. Signed-off-by: Dario Binacchi <dariobin@libero.it> Reviewed-by: Simon Glass <sjg@chromium.org>
* dtoc: Generate device instancesSimon Glass2021-03-221-0/+4
| | | | | | | | | | | | | Add support for generating a file containing udevice instances. This avoids the need to create these at run time. Update a test uclass to include a 'per_device_plat_auto' member, to increase test coverage. Add another tab to the driver_info output so it lines up nicely like the device-instance output. Signed-off-by: Simon Glass <sjg@chromium.org>
* dtoc: Generate uclass devicesSimon Glass2021-03-221-0/+1
| | | | | | | | | | Add support for generating a file containing uclass instances. This avoids the need to create these at run time. Update a test uclass to include a 'priv_auto' member, to increase test coverage. Signed-off-by: Simon Glass <sjg@chromium.org>
* sandbox: i2c: Rename driver names to work with of-platdataSimon Glass2021-03-222-3/+3
| | | | | | | Some of these do not follow the rules. Make sure the driver name matches the compatible string in all cases. Signed-off-by: Simon Glass <sjg@chromium.org>
* dtoc: Assign a sequence number to each nodeSimon Glass2021-03-221-2/+4
| | | | | | | | | | | | Now that we have the alias information we can assign a sequence number to each device in the uclass. Store this in the node associated with each device. This requires renaming the sandbox test drivers to have the right name. Note that test coverage is broken with this patch, but fixed in the next one. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: error handling dev_get_dma_range()Heinrich Schuchardt2021-03-221-2/+2
| | | | | | | | | goto after return has not effect. Calling of_node_put() in case of some errors and not for others is inconsistent. Fixes: 51bdb50904b ("dm: Introduce xxx_get_dma_range()") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* mmc: pci: Fix Kconfig dependencyBin Meng2021-03-221-0/+1
| | | | | | | | The PCI MMC driver depends on the generic MMC SDHCI driver, otherwise it does not compile. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* serial: mtk: rewrite the setbrg functionWeijie Gao2021-03-201-41/+33
| | | | | | | | | | | | | | | | | | Currently the setbrg logic of serial-mtk is messy, and should be rewritten. Also an option is added to make it possible to use highspeed-3 mode for all bauds. The new logic is: 1. If baud clock > 12MHz a) If baud <= 115200, highspeed-0 mode will be used (ns16550 compatible) b) If baud <= 576000, highspeed-2 mode will be used c) any bauds > 576000, highspeed-3 mode will be used 2. If baud clock <= 12MHz Forced highspeed-3 mode a) If baud <= 115200, calculates the divisor using DIV_ROUND_CLOSEST b) any bauds > 115200, the same as 1. c) Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* pinctrl: mt7629: add jtag function and pin groupWeijie Gao2021-03-201-0/+7
| | | | | | | The EPHY LEDs of mt7629 can be used as JTAG. This patch adds the jtag pin group to the pinctrl driver. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* pinctrl: mediatek: do not probe gpio driver if not enabledWeijie Gao2021-03-201-4/+8
| | | | | | | | | | | The mtk pinctrl driver is a combination driver with support for both pinctrl and gpio. When this driver is used in SPL, gpio support may not be enabled, and this will result in a compilation error. To fix this, macros are added to make sure gpio related code will only be compiled when gpio support is enabled. Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* pinctrl: mediatek: add get_pin_muxing ops for mediatek pinctrlSam Shih2021-03-201-0/+14
| | | | | | This patch add get_pin_muxing support for mediatek pinctrl drivers Signed-off-by: Sam Shih <sam.shih@mediatek.com>
* pinctrl: mediatek: fix wrong assignment in mtk_get_pin_nameSam Shih2021-03-201-1/+1
| | | | | | | This is a bug fix for mtk pinctrl common part. Appearently pins should be used instead of grps in mtk_get_pin_name(). Signed-off-by: Sam Shih <sam.shih@mediatek.com>
* pinctrl: renesas: Add support for R8A774C0Lad Prabhakar2021-03-164-0/+23
| | | | | | | | | | | Renesas RZ/G2E (a.k.a. r8a774c0) is pin compatible with R-Car E3 (a.k.a. r8a77990), however it doesn't have several automotive specific peripherals. This patch hooks R8A774C0 SoC with the pfc driver. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
* pinctrl: renesas: pfc-r8a77990: Sync PFC tables with Linux 5.11Lad Prabhakar2021-03-161-2/+85
| | | | | | | Sync the R8A77990 SoC PFC tables with Linux 5.11 , commit f40ddce88593. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
* Merge tag 'v2021.04-rc4' into nextTom Rini2021-03-1552-228/+306
|\ | | | | | | Prepare v2021.04-rc4
| * Merge tag 'u-boot-stm32-20210312' of ↵Tom Rini2021-03-1513-46/+56
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-stm - Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver - stm32mp1_trusted_defconfig rely on SCMI support - Remove the nand MTD configuration for NOR boot in stm32mp1 board - STM32programmer update - Bsec: manage clock when present in device tree - stm32mp15: move bootdelay configuration in defconfig - Update for stm32 dsi and dw_mipi_dsi - STM32 MCU's cleanup - Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags - Update stm32mp1 doc
| | * video: dw_mipi_dsi: update log of dphy_enableYannick Fertre2021-03-111-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DSI phy can be turned on from the DSI digital interface in the dphy_enable() function or from a dedicated DSI phy "wrapper" in phy_ops->init() function. If the STM32MP1 case, the wrapper is used then the dphy_enable() "warning" traces are not relevant. This patch moves these "warning" traces to "debug" traces so they are still available for DSI phy based on the digital interface in debug logging mode, but not there in normal mode for both cases. Note: The related Linux kernel driver uses a "debug" message too. Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * video: dw_mipi_dsi: missing device to log debugYannick Fertre2021-03-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Missing udevice to struct dw_mipi_dsi to log trace. Signed-off-by: Yannick Fertre <yannick.fertre@foss.st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Acked-by: Yannick Fertre <yannick.fertre@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * video: stm32: remove all child of DSI bridge when its probe failedPatrick Delaunay2021-03-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the child device of the STM32 DSI bridge when the driver probe failed to stop futher probe request on panels used with STMicroelectronics board (orisetech_otm8009a.c or raydium-rm68200.c driver). This patch avoid the trace "cannot get reset GPIO" when STM32MP157 device tree is used on stm32MP151 SOC without DSI support. In this hw_version value is 0, as DSI bridge is absent and the panel ofdata_to_platdata is called for each try of panel probe, the gpio reset pin is requested but after dsi father probe failed). For the next request, the PANEL ofdata_to_platdata failed as the gpio is already used. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * scmi: cosmetic: reorder include filesPatrick Delaunay2021-03-112-3/+2
| | | | | | | | | | | | | | | | | | | | | Reorder include files in expected order. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * scmi: define LOG_CATEGORYPatrick Delaunay2021-03-116-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Define LOG_CATEGORY to allow filtering with log command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * scmi: Include device_compat.hPatrick Delaunay2021-03-111-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | Include the file needed for log function prototype, this patch solves the compilation issue for undefined reference to `dev_err'. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * clk: stm32mp1: gets root clocks from fdtEtienne Carriere2021-03-111-39/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change makes stm32mp1 clock driver to get the root clocks reference from the device node in the FDT rather than fetching straight these clocks by their name. Driver now stores the clock reference and use it to know if a root clock is present, get its rate or gets its related udevice reference. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| | * mtd: spinand: Add WATCHDOG_RESET() in spinand_mtd_read/write()Patrice Chotard2021-03-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case of big area read/write on spi nand, watchdog timeout may occurs. To fix that, add WATCHDOG_RESET() in spinand_mtd_read() and spinand_mtd_write() to ensure that watchdog is reset. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| | * mtd: nand: Add WATCHDOG_RESET() in nanddev_mtd_erase()Patrice Chotard2021-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | In case of big area erased on nand, watchdog timeout may occurs. To fix that, add WATCHDOG_RESET() in nanddev_mtd_erase() to ensure that watchdog is reset. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| | * spi: stm32_qspi: Add WATCHDOG_RESET in _stm32_qspi_read_fifo()Patrice Chotard2021-03-111-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of reading large area and memory-map mode is misconfigured (memory-map size declared lower than the real size of the memory chip) watchdog can be triggered. Add WATCHDOG_RESET() in _stm32_qspi_read_fifo to fix it. Issue reproduced with stm32mp157c-ev1 board and memory map size set to 1, with following command: sf read 0xC0000000 0 0x4000000 Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| | * mtd: spi-nor: Add WATCHDOG_RESET() in spi_nor_core callbacksPatrice Chotard2021-03-111-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In case of big area write/erase on spi nor, watchdog timeout may occurs. Issue reproduced on stm32mp157c-ev1 with following commands: sf write 0xC0000000 0 0x3000000 or sf erase 0 0x1000000 Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | arm: mvebu: a38x: Remove dead code ARMADA_39XPali Rohár2021-03-123-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Config option ARMADA_39X is never set so remove all dead code hidden under ifdef CONFIG_ARMADA_39X blocks. Also remove useless checks for CONFIG_ARMADA_38X define as this macro is always defined for a38x code path. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * | arm: a37xx: pci: Implement workaround for the readback value of VEND_IDPali Rohár2021-03-121-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it should read 11ABh. The firmware can write the correct value, 11ABh, through VEND_ID (RD0076044h [15:0]). Implement this workaround in U-Boot PCIe controller driver aardvark for both PCI vendor id and PCI subsystem vendor id. This change affects PCI vendor id of PCIe root bridge emulated by Linux kernel. With this change Linux kernel reports correct vendor id 11AB. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
| * | ddr: marvell: axp: fix array types have different bounds warningMarek Behún2021-03-122-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The arrays `pbs_dq_mapping`, `div_ratio1to1` and `div_ratio2to1` have different bounds declared in header files where these variables are also defined from the ones declared in source files. This causes the compiler to complain (when building with LTO): ddr3_sdram.c:24:12: warning: type of ‘pbs_dq_mapping’ does not match original declaration [-Wlto-type-mismatch] ddr3_patterns_64bit.h:911:5: note: array types have different bounds ddr3_patterns_64bit.h:911:5: note: ‘pbs_dq_mapping’ was previously declared here ddr3_dfs.c:45:11: warning: type of ‘div_ratio1to1’ does not match original declaration [-Wlto-type-mismatch] ddr3_axp_vars.h:167:4: note: array types have different bounds ddr3_axp_vars.h:167:4: note: ‘div_ratio1to1’ was previously declared here ddr3_dfs.c:46:11: warning: type of ‘div_ratio2to1’ does not match original declaration [-Wlto-type-mismatch] ddr3_axp_vars.h:196:4: note: array types have different bounds ddr3_axp_vars.h:196:4: note: ‘div_ratio2to1’ was previously declared here CI managed to trigger this as an error when compiling with LTO for AXP. Fix this by using values from the header files, which seem to be the correct ones. Signed-off-by: Marek Behún <marek.behun@nic.cz>
| * | ddr: marvell: axp: align signature of mv_xor_mem_init() with a38xMarek Behún2021-03-122-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In arch/arm/mach-mvebu/dram.c we always include axp's xor.h for common XOR definitions, regardless whether we compile for axp or a38x. But the declaration of this function has a different signature in axp's xor.h from the one used in a38x' implementation - one parameter is u64 instead of u32. This can result in wrong argument's being passed to that function on a38x with no one the wiser. I discovered this when building U-Boot for Turris Omnia with LTO. The compiler complains about the different signatures being thrown into the same linking process: axp/xor.h:67:5: warning: type of ‘mv_xor_mem_init’ does not match original declaration [-Wlto-type-mismatch] 67 | int mv_xor_mem_init(u32 chan, u32 start_ptr, u32 block_size, | ^ a38x/xor.c:165:5: note: type mismatch in parameter 3 165 | int mv_xor_mem_init(u32 chan, u32 start_ptr, unsigned long long | ^ a38x/xor.c:165:5: note: type ‘long long unsigned int’ should match type ‘u32’ Fix this by changing the type of the block_size argument in the axp's implementation and header file to the one used in a38x (and upstream mv-ddr-marvell). Signed-off-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
| * | ddr: marvell: a38x: Sync code with Marvell mv-ddr-marvell repositoryPali Rohár2021-03-1210-40/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This syncs drivers/ddr/marvell/a38x/ with the master branch of repository https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git up to the commit 7c351731d196 ("Merge pull request #29 from pali/sync-a38x-uboot"). This patch was created by following steps: 1. Replace all a38x files in U-Boot tree by files from upstream github Marvell mv-ddr-marvell repository. 2. Run following command to omit portions not relevant for a38x and ddr3: files=drivers/ddr/marvell/a38x/* sed 's/#if defined(CONFIG_ARMADA_38X) || defined(CONFIG_ARMADA_39X)/#ifdef TRUE/' -i $files unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 -UCONFIG_APN806 \ -UCONFIG_MC_STATIC -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_PHY_STATIC_PRINT -UCONFIG_CUSTOMER_BOARD_SUPPORT \ -UCONFIG_A3700 -UA3900 -UA80X0 -UA70X0 -DTRUE $files 3. Manually omit SPDX-License-Identifier changes from this patch as upstream license in upstream github repository contains long license texts and U-Boot is using just SPDX-License-Identifier. After applying this patch, a38x ddr3 code in upstream Marvell github repository and in U-Boot would be fully identical. So in future applying above steps could be used to sync code again. The only change in this patch is removal of dead code and some fixes with include files. Signed-off-by: Pali Rohár <pali@kernel.org> Tested-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
| * | ddr: marvell: a38x: Add more space for additional info from SPDSujeet Baranwal2021-03-121-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit 258be123226f8f5cd516b7813fe201fb7d7416e9 upstream. At this moment, only page 0 of SPD is being read but to support smbios, we need to read page 1 also which has more info. In order to do that, we need to allocate more space. Signed-off-by: Sujeet Baranwal <sujeet.baranwal@cavium.com> Tested-by: sa_ip-sw-jenkins <sa_ip-sw-jenkins@marvell.com> Reviewed-by: Sujeet Kumar Baranwal <Sujeet.Baranwal@cavium.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Marek Behún <marek.behun@nic.cz> Tested-by: Chris Packham <judge.packham@gmail.com>
| * | usb: mtu3: flush cache for next GPDChunfeng Yun2021-03-101-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | When flush cache of the current GPD and resume QMU, the controller will try to access the next GPD after processing the current one, if not flush the next GPD, the controller may get wrong GPD status. Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
| * | x86: Move INTEL_ACPIGEN to arch/x86Simon Glass2021-03-091-9/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This option is better placed in the x86 code since it is not generic enough to be in the core code. Move it. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
| * | Merge tag 'u-boot-amlogic-20210308' of ↵Tom Rini2021-03-081-7/+7
| |\ \ | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic - button: adc: fix treshold typo - configs: meson64: add fdtoverlay_addr_r
| | * | button: adc: fix treshold typoNeil Armstrong2021-03-081-7/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix the treshold typo in code by threshold. Fixes: c0165c85c3 ("button: add a simple Analog to Digital Converter device based button driver") Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Acked-by: Marek Szyprowski <m.szyprowski@samsung.com>
| * | | arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim2021-03-083-5/+5
| |/ / | | | | | | | | | | | | | | | Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
| * | dm: sysreset: Add a Kconfig option for the 'reset' commandBin Meng2021-03-052-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | sysreset uclass driver provides an implementation of 'reset' command using the sysreset_ APIs unconditionally. It also supports the 'poweroff' command using the sysreset_ APIs, but under a Kconfig option CONFIG_SYSRESET_CMD_POWEROFF. Let's do the same for the 'reset' command, by introducing a new Kconfig option CONFIG_SYSRESET_CMD_RESET, and set it to on by default, to allow a board that don't have a sysreset reset driver yet, but have a sysreset poweroff driver to compile without any issue. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | gpio: mpc8xxx: Support controller register physical address beyond 32-bitBin Meng2021-03-051-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | dev_read_addr_size_index() returns fdt_addr_t which might be a 64-bit physical address. This might be true for some 85xx SoCs whose CCSBAR is mapped beyond 4 GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | virtio: Fix VirtIO BLK driver dependencyBin Meng2021-03-051-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | The VirtIO BLK driver depends on the blk uclass driver. Add the dependency in the Kconfig. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: mpc85xx: Support 64-bit bus and cpu addressBin Meng2021-03-051-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present the driver only supports 32-bit bus and cpu address. The controller's outbound registers/fields for extended address are not programmed. Let's program them to support 64-bit bus and cpu address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: mpc85xx: Support controller register physical address beyond 32-bitBin Meng2021-03-051-3/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | devfdt_get_addr_index() returns fdt_addr_t which might be a 64-bit physical address. Use map_physmem() to return the virtual address that can be used by a 32-bit machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: mpc85xx: Wrap LAW programming with CONFIG_FSL_LAWBin Meng2021-03-051-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For the QEMU ppce500 machine, LAW registers are not implemented hence CONFIG_FSL_LAW is not turned on and all LAW APIs are not available. We should wrap all LAW registers programming in the mpc85xx PCI driver with CONFIG_FSL_LAW. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | pci: fsl_pci_init: Dynamically allocate the PCI regionsBin Meng2021-03-051-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions") changes 'struct pci_controller'.regions from pre-allocated array of regions to dynamically allocated, which unfortunately broken lots of boards that still use the non-DM PCI driver. This patch changes the non-DM fsl_pci_init driver to dynamically allocate the regions, just like what's done in the pci uclass driver. Fixes: e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
| * | serial: ns16550: Handle zero <clock-frequency> valueBin Meng2021-03-031-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A working device tree node of ns16550 should never be populated with value zero for the <clock-frequency> property. Unfortunately this is the case for the QEMU ppce500 target. Let's try to assign plat->clock to CONFIG_SYS_NS16550_CLK as the last resort to handle such case. This commit should be reverted when: - The following QEMU patch [1] is merged, and - U-Boot CI has upgraded its QEMU version that contains the fix [1] http://patchwork.ozlabs.org/project/qemu-devel/patch/1612362288-22216-2-git-send-email-bmeng.cn@gmail.com/ Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-06-22 12:34:34 +0000