summaryrefslogtreecommitdiffstats
path: root/drivers/timer/Kconfig
Commit message (Collapse)AuthorAgeFilesLines
* timer: Add _TIMER suffix to Andes PLMT KconfigSean Anderson2020-10-261-1/+1
| | | | | | | | This matches the naming scheme of other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* riscv: Move Andes PLMT driver to drivers/timerSean Anderson2020-10-261-0/+7
| | | | | | | | | This is a regular timer driver, and should live with the other timer drivers. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* Merge tag 'u-boot-atmel-2021.01-a' of ↵Tom Rini2020-10-051-0/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.
| * timer: mchp-pit64b: add support for pit64bClaudiu Beznea2020-09-281-0/+7
| | | | | | | | | | | | | | | | | | Add support for Microchip PIT64B timer. The timer is 64 bit length and is used as a free running counter (in continuous mode with highest values for period registers). The clock feeding the timer would be no more than 12.5MHz. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | riscv: Rework riscv timer driver to only support S-modeSean Anderson2020-09-301-2/+2
|/ | | | | | | | | | | | | | | | | | | | | | | | The riscv-timer driver currently serves as a shim for several riscv timer drivers. This is not too desirable because it bypasses the usual timer selection via the driver model. There is no easy way to specify an alternate timing driver, or have the tick rate depend on the cpu's configured frequency. The timer drivers also do not have device structs, and so have to rely on storing parameters in gd_t. Lastly, there is no initialization call, so driver init is done in the same function which reads the time. This can result in confusing error messages. To a user, it looks like the driver failed when trying to read the time, whereas it may have failed while initializing. This patch removes the shim functionality from the riscv-timer driver, and has it instead implement the former rdtime.c timer driver. This is because existing u-boot users who pass in a device tree (e.g. qemu) do not create a timer device for S-mode u-boot. The existing behavior of creating the riscv-timer device in the riscv cpu driver must be kept. The actual reading of the CSRs has been redone in the style of Linux's get_cycles64. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Rick Chen <rick@andestech.com>
* timer: Add driver for Nomadik Multi Timer Unit (MTU)Stephan Gerhold2020-01-221-0/+9
| | | | | | | | | | The Nomadik Multi Timer Unit (MTU) provides 4 decrementing free-running timers. It is used in ST-Ericsson Ux500 SoCs. The driver uses the first timer to implement UCLASS_TIMER. Signed-off-by: Stephan Gerhold <stephan@gerhold.net> Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
* x86: timer: Reduce timer code size in TPL on Intel CPUsSimon Glass2019-12-151-0/+9
| | | | | | | | | | | | | | | Most of the timer-calibration methods are not needed on recent Intel CPUs and just increase code size. Add an option to use the known-good way to get the clock frequency in TPL. Size reduction is about 700 bytes. Note that version 1 of this commit caused bootstage to crash since the CPU was not identified. This is corrected by changes previously applied to make sure that the CPU is identified before spl_init() is called, such as 39146a2e0b x86: Move CPU init to before spl_init() Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: timer: use a timer base of 0Simon Glass2019-12-151-0/+14
| | | | | | | | | | | | | | | | On x86 platforms the timer is reset to 0 when the SoC is reset. Having this as the timer base is useful since it provides an indication of how long it takes before U-Boot is running. When U-Boot sets the timer base to something else, time is lost and we no-longer have an accurate account of the time since reset. This particularly affects bootstage. Change the default to not read the timer base, leaving it at 0. Add an option for when U-Boot is the secondary bootloader. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* timer: renesas: Add RZ/A1 R7S72100 OSTM timer driverMarek Vasut2019-05-071-0/+7
| | | | | | | | | | Add OSTM timer driver for RZ/A1 SoC. The IP is very different from the R-Car Gen2/Gen3 one already present in the tree, hence a custom driver. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Chris Brandt <chris.brandt@renesas.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* timer: Add generic driver for RISC-V privileged architecture defined timerBin Meng2018-12-181-0/+7
| | | | | | | | | | | | | | | | | | | | | | RISC-V privileged architecture v1.10 defines a real-time counter, exposed as a memory-mapped machine-mode register - mtime. mtime must run at constant frequency, and the platform must provide a mechanism for determining the timebase of mtime. The mtime register has a 64-bit precision on all RV32, RV64, and RV128 systems. Different platform may have different implementation of the mtime block hence an API riscv_get_time() is required by this driver for platform codes to hide such implementation details. For example, on some platforms mtime is provided by the CLINT module, while on some other platforms a simple 'rdtime' can be used to get the timer counter. With this timer driver the U-Boot timer functionalities like delay works correctly now. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Lukas Auer <lukas.auer@aisec.fraunhofer.de> Reviewed-by: Anup Patel <anup@brainfault.org>
* timer: MediaTek: add timer driver for MediaTek SoCsRyder Lee2018-11-281-0/+7
| | | | | | | | | This patch adds clock source and clock event for the timer found on the Mediatek SoCs. Signed-off-by: Ryder Lee <ryder.lee@mediatek.com> Tested-by: Matthias Brugger <matthias.bgg@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* timer: Sort Kconfig driver entriesBin Meng2018-11-141-55/+55
| | | | | | | This is currently out of order. Sort it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: tsc: Introduce config option for early timer frequencyBin Meng2018-10-221-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | So far the TSC timer driver supports trying hardware calibration first and using device tree as last resort for its running frequency as the normal timer. However when it is used as the early timer, it only supports hardware calibration and if it fails, the driver just panics. This introduces a new config option to specify the early timer frequency in MHz and it should be equal to the value described in the device tree. Without this patch, the travis-ci testing on QEMU x86_64 target fails each time after it finishes the 'bootefi selftest' as the test.py see an error was emitted on the console like this: TSC frequency is ZERO resetting ... ### ERROR ### Please RESET the board ### It's strange that this error is consistently seen on the travis-ci machine, but only occasionally seen on my local machine (maybe 1 out of 10). Since QEMU x86_64 target enables BOOTSTAGE support which uses early timer, with this fix it should work without any failure. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Enable CONFIG_TIMER_EARLY with bootstageSimon Glass2018-10-221-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In initr_bootstage() we call bootstage_mark_name() which ends up calling timer_get_us(). This call happens before initr_dm(), which inits driver model. On x86 we set gd->timer to NULL in the transition from board_init_f() to board_init_r(). See board_init_f_r() for this assignment. So U-Boot knows there is no timer available in the period immediately after relocation. On x86 the timer_get_us() call is implemented as calls to get_ticks() and get_tbclk(). Both of these call dm_timer_init() to set up the timer, if gd->timer is NULL and the early timer is not available. However dm_timer_init() cannot succeed before initr_dm() is called. So it seems that on x86 if we want to use CONFIG_BOOTSTAGE we must enable CONFIG_TIMER_EARLY. Update the Kconfig to handle this. Note: On most architectures we can rely on the pre-relocation memory still being available, so that gd->timer pointers to a valid timer device and everything works correctly. Admittedly this is not strictly correct since the timer device is set up by pre-relocation U-Boot, but normally this is fine. On x86 the 'CAR' (cache-as-RAM) memory used by pre-relocation U-Boot disappears in board_init_f_r() and any attempt to access it will hang. This is the reason why we must mark the timer as invalid when we get to board_init_f_r(). Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* timer: Add MPC83xx timer driverMario Six2018-09-181-0/+7
| | | | | | Add a timer driver for the MPC83xx architecture. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* timer: dw-apb: Add Designware APB timer driverMarek Vasut2018-08-241-0/+7
| | | | | | | | | | Add timer driver for the Designware APB Timer IP. This is present for example on the Altera SoCFPGA chips. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Ley Foon Tan <ley.foon.tan@intel.com>
* timer: Add Cadence TTC timer counter supportMichal Simek2018-05-111-0/+7
| | | | | | This driver was tested on Xilinx ZynqMP SoC. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* timer: stm32: Add timer support for STM32 SoCs familyPatrice Chotard2018-03-131-0/+7
| | | | | | | | This timer driver is using GPT Timer (General Purpose Timer) available on all STM32 SOCs family. This driver can be used on STM32F4/F7 and H7 SoCs family Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* atcpit100: timer: Remove arch dependency.Rick Chen2017-11-301-1/+1
| | | | | | | | | | ATCPIT100 is often used in AE3XX platform which is based on NDS32 architecture recently. But in the future Andestech will have AE250 platform which is embeded ATCPIT100 timer based on RISCV architecture. Signed-off-by: Rick Chen <rick@andestech.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* ae3xx: timer: Rename AE3XX to ATCPIT100Rick Chen2017-11-301-3/+4
| | | | | | | | | | ATCPIT100 is Andestech timer IP which is embeded in AE3XX and AE250 boards. So rename AE3XX to ATCPIT100 will be more make sence. Signed-off-by: rick <rick@andestech.com> Signed-off-by: Rick Chen <rickchen36@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* driver: timer: Add the Atmel PIT timer driverWenyou.Yang@microchip.com2017-08-261-0/+8
| | | | | | | Add the new Atmel PIT timer driver, which supports the driver model and device tree. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com>
* rockchip: timer: add device-model timer driver for RK3368 (and similar)Philipp Tomsich2017-08-131-0/+7
| | | | | | | | | | | | | | This adds a device-model driver for the timer block in the RK3368 (and similar devices that share the same timer block, such as the RK3288) for the down-counting (i.e. non-secure) timers. This allows us to configure U-Boot for the RK3368 in such a way that we can run with the secure timer inaccessible or uninitialised (note that the ARMv8 generic timer does not count, if the secure timer is not enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* dm: timer: normalise SPL and TPL supportPhilipp Tomsich2017-08-131-0/+18
| | | | | | | | | | | | | | | | | | To fully support DM timer in SPL and TPL, we need a few things cleaned up and normalised: - inclusion of the uclass and drivers should be an all-or-nothing decision for each stage and under control of $(SPL_TPL_)TIMER instead of having the two-level configuration with TIMER and $(SPL_TPL_)TIMER_SUPPORT - when $(SPL_TPL_)TIMER is enabled, the ARMv8 generic timer code can not be compiled in This normalises configuration to $(SPL_TPL_)TIMER and moves the config options to drivers/timer/Kconfig (and cleans up the collateral damage to some defconfigs that had SPL_TIMER_SUPPORT enabled). Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* x86: kconfig: Select TIMER and X86_TSC_TIMERBin Meng2017-08-011-1/+0
| | | | | | | | | Without a timer, U-Boot just doesn't boot. This is not something we can turn off. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* nds32: Support AE3XX platform.rick2017-05-221-3/+9
| | | | | | Support Andestech AE3xx platform: serial, timer device tree flow. Signed-off-by: rick <rick@andestech.com>
* nds32: Support AG101P timer DM.rick2017-05-221-0/+6
| | | | | | Support AG101P timer device tree flow. Signed-off-by: rick <rick@andestech.com>
* drivers: timer: Introduce ARC timer driverVlad Zakharov2017-03-241-0/+9
| | | | | | | | | | | | | | | This commit introduces timer driver for ARC. ARC timers are configured via ARC AUX registers so we use special functions to access timer control registers. This driver allows utilization of either timer0 or timer1 depending on which one is available in real hardware. Essentially only existing timers should be mentioned in board's Device Tree description. Signed-off-by: Vlad Zakharov <vzakhar@synopsys.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* STiH410: Add STi timer driverPatrice Chotard2017-03-141-0/+7
| | | | | | | Add ARM global timer based timer Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* aspeed: Add drivers common to all Aspeed SoCsmaxims@google.com2017-01-281-0/+12
| | | | | | | | | | | | | | | | | Add support for Watchdog Timer, which is compatible with AST2400 and AST2500 watchdogs. There is no uclass for Watchdog yet, so the driver does not follow the driver model. It also uses fixed clock, so no clock driver is needed. Add support for timer for Aspeed ast2400/ast2500 devices. The driver actually controls several devices, but because all devices share the same Control Register, it is somewhat difficult to completely decouple them. Since only one timer is needed at the moment, this should be OK. The timer uses fixed clock, so does not rely on a clock driver. Add sysreset driver, which uses watchdog timer to do resets and particular watchdog device to use is hardcoded (0) Reviewed-by: Simon Glass <sjg@chromium.org>
* timer: Provide an early timerSimon Glass2016-02-261-0/+10
| | | | | | | | | | In some cases the timer must be accessible before driver model is active. Examples include when using CONFIG_TRACE to trace U-Boot's execution before driver model is set up. Enable this option to use an early timer. These functions must be supported by your timer driver: timer_early_get_count() and timer_early_get_rate(). Signed-off-by: Simon Glass <sjg@chromium.org>
* drivers: timer: omap_timer: add timer driver for omap devices based on dmMugunthan V N2016-01-201-0/+6
| | | | | | | Adding a timer driver for omap devices based on driver model and device tree. Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com>
* x86: tsc: Move tsc_timer.c to drivers/timerBin Meng2015-12-011-0/+7
| | | | | | | | To group all dm timer drivers together, move tsc timer to drivers/timer directory. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* dm: timer: Fix several nitsBin Meng2015-12-011-6/+6
| | | | | | | | This changes 'Timer' to 'timer' at several places. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* sandbox: add a sandbox timer and basic testThomas Chou2015-11-191-0/+7
| | | | | | | | Add a sandbox timer which get time from host os and a basic test. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Reviewed-by: Simon Glass <sjg@chromium.org>
* nios2: convert altera timer to driver modelThomas Chou2015-10-231-0/+7
| | | | | | | Convert altera timer to driver model. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com>
* dm: implement a Timer uclassThomas Chou2015-10-231-0/+12
Implement a Timer uclass to work with lib/time.c. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2026-01-01 16:51:26 +0000