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* spi: kirkwood: prevent limiting speed to 0Grzegorz Jaszczyk2021-05-161-1/+1
| | | | | | | | | | | | | | After commit 1fe929ed497bcc8975be8d37383ebafd22b99dd2 ("spi: kirkwood: prevent configuring speed exceeding max controller freq") the spi frequency could be set to 0 on platform where spi-max-frequency is not defined (e.g. on armada-388-gp). Prevent limiting speed in mentioned cases. Signed-off-by: Grzegorz Jaszczyk <jaz@semihalf.com> Tested-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Marcin Wojtas <marcin@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* spi: kirkwood: prevent configuring speed exceeding max controller freqMarcin Wojtas2021-05-161-0/+7
| | | | | | | | | | | This patch adds a limitation in the kirkwood_spi driver set_speed hook, which prevents setting too high transfer speed. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* spi: kirkwood: support extended baud ratesKen Ma2021-05-161-5/+55
| | | | | | | | | | | | | | | | The Armada SoC family implementation of this SPI hardware module has extended the configuration register to allow for a wider range of SPI clock rates. Specifically the Serial Baud Rate Pre-selection bits in the SPI Interface Configuration Register now also use bits 6 and 7 as well. Modify the baud rate calculation to handle these differences for the Armada case. Potentially a baud rate can be setup using a number of different pre-scalar and scalar combinations. This code tries all possible pre-scalar divisors (8 in total) to try and find the most accurate set. Signed-off-by: Ken Ma <make@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* atcspi200: Add timeout mechanism in spi_xfer()Dylan Jhong2021-05-051-2/+8
| | | | | | | | | Adding timeout mechanism to avoid spi driver from stucking in the while loop in __atcspi200_spi_xfer(). Signed-off-by: Dylan Jhong <dylan@andestech.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com> Reviewed-by: Rick Chen <rick@andestech.com>
* spi: zynqmp: Remove gd referenceMichal Simek2021-04-291-3/+0
| | | | | | gd is not used in this file that's why doesn't make sense to declare it. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge tag 'xilinx-for-v2021.07' of ↵Tom Rini2021-03-311-5/+3
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.07 net: - Fix gem PCS support spi: - Small trivial fixes zynq: - Enable time/timer commands - Update bitmain platform - Several DT changes zynqmp: - Update clock driver - mini config alignments - Add/update psu_init for zcu208/zcu216/zc1275 - Several DT changes - Enable efi debug command (also for Versal)
| * spi: xilinx_spi: Trivial fixes in axi qspi driverT Karthik Reddy2021-03-301-5/+3
| | | | | | | | | | | | | | | | | | Use __func__ instead for function name in debug. Use Linux style u32 instead of uint32_t. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | spi: spi-uclass: Add support to manually relocate spi memory opsT Karthik Reddy2021-03-271-0/+11
|/ | | | | | | | | | Add spi memory operations to relocate manually when CONFIG_NEEDS_MANUAL_RELOC is enabled. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Acked-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com>
* spi: stm32_qspi: Add WATCHDOG_RESET in _stm32_qspi_read_fifo()Patrice Chotard2021-03-111-0/+2
| | | | | | | | | | | | | | | In case of reading large area and memory-map mode is misconfigured (memory-map size declared lower than the real size of the memory chip) watchdog can be triggered. Add WATCHDOG_RESET() in _stm32_qspi_read_fifo to fix it. Issue reproduced with stm32mp157c-ev1 board and memory map size set to 1, with following command: sf read 0xC0000000 0 0x4000000 Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* spi: nxp_fspi: Fix error reportingAdam Ford2021-02-261-2/+2
| | | | | | | | | | | | On the i.MX8M Mini, ret = clk_set_rate() sets ret to the value of the rate the clock was able to set. When checking for errors, it only checks that it is not NULL. Since positive numbers are not errors, only check for negative numbers when handling errors. Fixes: 383fded70c4f ("spi: nxp_fspi: new driver for the FlexSPI controller") Signed-off-by: Adam Ford <aford173@gmail.com> Reviewed-by: Pratyush Yadav <p.yadav@ti.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* spi: imx: Implement set_speedMarek Vasut2021-02-261-1/+4
| | | | | | | | | The set_speed() callback should configure the bus speed, make it so. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* Merge tag 'xilinx-for-v2021.04-rc3' of ↵Tom Rini2021-02-233-109/+84
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name
| * spi: zynqmp_gqspi: fix set_speed bug on multiple runsBrandon Maier2021-02-231-12/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If zynqmp_qspi_set_speed() is called multiple times with the same speed, then on the second call it will skip recalculating the baud_rate_val as it assumes the speed is already configured correctly. But it will still write the baud_rate_val to the configuration register and call zynqmp_gqspi_set_tapdelay(). Because it skipped recalculating the baud_rate_val, it will use the initial value of 0 . This causes the driver to run at maximum speed which for many spi flashes is too fast and causes data corruption. Instead only write out a new baud_rate_val if we have calculated the correct baud_rate_val. This opens up another issue with the "if (speed == 0)", we don't save off the new plat->speed_hz value when setting the baud rate on the speed=0 path. Instead mimic what the Linux zynqmp gqspi driver does, and have speed==0 just use the same calculation as a normal speed. That will cause the baud_rate_val to use the slowest speed possible, which is the safest option. Signed-off-by: Brandon Maier <brandon.maier@rockwellcollins.com> CC: jagan@amarulasolutions.com CC: michal.simek@xilinx.com CC: Ashok Reddy Soma <ashokred@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * clk: zynq: Add dummy clock enable functionMichal Simek2021-02-233-3/+3
| | | | | | | | | | | | | | | | | | A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * spi: zynqmp_gqspi: support dual and quad modeBrandon Maier2021-02-031-94/+70
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The dm_spi_ops.xfer() API does not support dual and quad SPI modes. It also doesn't allow the zynqmp_gqspi driver to calculate the correct number of dummy cycles for some NOR ops (as doing so also requires the buswidth). Port the zynqmp_gqspi driver to spi_controller_mem_ops, which gives us the buswidth values to correctly support all SNOR_PROTO_X_X_X commands and to properly calculate dummy cycles. Signed-off-by: Brandon Maier <brandon.maier@rockwellcollins.com> CC: jagan@amarulasolutions.com CC: michal.simek@xilinx.com CC: Ashok Reddy Soma <ashokred@xilinx.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-1526-0/+26
|\ \ | | | | | | | | | - Merge the patch to take <asm/global_data.h> out of <common.h>
| * | common: Drop asm/global_data.h from common headerSimon Glass2021-02-0226-0/+26
| |/ | | | | | | | | | | | | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | spi: fsl_qspi: apply the same settings for LS1088 as LS208xMathew McBride2021-02-081-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | The LS1088 requires the same QUADSPI_QURIK_BASE_INTERNAL workaround as the LS208x and also has a 64 byte TX buffer. With the previous settings SPI-NAND reads over AHB were corrupted. Fixes: 91afd36f3802 ("spi: Transform the FSL QuadSPI driver to use the SPI MEM API") Signed-off-by: Mathew McBride <matt@traverse.com.au> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | spi: fsl_qspi: Ensure width is respected in spi-mem operationsMathew McBride2021-02-081-1/+1
|/ | | | | | | | | | | | | | | | | | | Adapted from kernel commit b0177aca7aea From: Michael Walle <michael@walle.cc> Make use of a core helper to ensure the desired width is respected when calling spi-mem operators. Otherwise only the SPI controller will be matched with the flash chip, which might lead to wrong widths. Also consider the width specified by the user in the device tree. Fixes: 91afd36f38 ("spi: Add a driver for the Freescale/NXP QuadSPI controller") Signed-off-by: Michael Walle <michael@walle.cc> Link: https://lore.kernel.org/r/20200114154613.8195-1-michael@walle.cc Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Mathew McBride <matt@traverse.com.au> [adapt for U-Boot] Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* spi: mtk_snor: add support for MTK SPI NOR controllerSkyLake.Huang2021-01-293-0/+571
| | | | | | | | | | | | | | This patch adds support for MTK SPI NOR controller, which you can see on mt7622 & mt7629. 1. This controller is designed only for SPI NOR. We can't adjust its bus clock dynamically. Set clock in dts instead. 2. This controller only supports 1-1-1 write mode. 3. Remove mtk_snor_match_read() since upper SPI-MEM layer already handles command. 4. sf read/write/update commands are tested with this driver. Signed-off-by: SkyLake.Huang <skylake.huang@mediatek.com>
* Merge tag 'mips-pull-2021-01-24' of ↵Tom Rini2021-01-253-0/+289
|\ | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - MIPS: add support for Mediatek MT7620 SoCs
| * spi: add spi controller support for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+289
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds spi controller support for MediaTek MT7620 SoC. The SPI controller supports two chip selects. These two chip selects are implemented as two separate register groups, but they share the same bus (DI/DO/CLK), only CS pins are dedicated for each register group. Appearently these two register groups cannot operates simulataneously so they are implemented as one controller. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* | spi: imx: Use clock framework if enabledMarek Vasut2021-01-231-0/+12
| | | | | | | | | | | | | | | | | | In case the clock framework is enabled, enable the SPI controller clock and obtain max frequency from the clock framework. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de>
* | spi: imx: Define register bits in the driverMarek Vasut2021-01-231-0/+76
| | | | | | | | | | | | | | | | | | | | The CSPI/ECSPI register bits do not differ between newer SoCs, instead of having multiple copies of the same thing for each iMX SoC, define the bits in the driver. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Stefano Babic <sbabic@denx.de>
* | spi: nxp_fspi: Enable support for nxp,imx8mm-fspiAdam Ford2021-01-231-0/+9
|/ | | | | | | The i.MX8M Mini can use the FlexSPI driver. Add support for it to the driver. Signed-off-by: Adam Ford <aford173@gmail.com>
* dm: fix build errors generated by last mergesDario Binacchi2021-01-151-1/+1
| | | | | | | | | | | | | | | Something was wrong in the merge process into the mainline. Some added patches access driver structure fields and functions that have been modified by previous patches. The patch renames: - dev_get_platdata to dev_get_plat - dev_get_uclass_platdata to dev_get_uclass_plat - ofdata_to_platdata to of_to_plat - plat_data_alloc_size to plat_auto - priv_auto_alloc_size to priv_auto - video_uc_platdata to video_uc_plat Signed-off-by: Dario Binacchi <dariobin@libero.it>
* spi: stm32_qspi: migrate trace to dev and log macroPatrick Delaunay2021-01-131-21/+25
| | | | | | | | | | Change debug/pr_* to log_* or dev_* macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* spi: stm32_spi: migrate trace to dev and log macroPatrick Delaunay2021-01-131-14/+17
| | | | | | | | | | | Change debug/pr_debug to log_debug or dev_dbg macro and define LOG_CATEGORY. Remove the "%s:" __func__ header as it is managed by dev macro (dev->name is displayed) or log macro (CONFIG_LOGF_FUNC). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* spi: omap3_spi: Fix speed and mode selectionVignesh Raghavendra2021-01-121-3/+14
| | | | | | | | | | | | McSPI IP provides per CS specific speed and mode selection. Therefore it is possible to apply these settings only after CS is known. But set_speed and set_mode can be called without bus being claimed, this would lead driver to set up wrong CS (or previously used CS). Fix this by apply set_speed and set_mode only if bus is already claimed. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Tested-by: Miquel Raynal <miquel.raynal@bootlin.com>
* spi: ti_qspi: Fix "spi-max-frequency" error path in ti_qspi_ofdata_to_platdataOvidiu Panait2021-01-121-2/+2
| | | | | | | | | | | | | | | struct ti_qspi_priv->max_hz is declared as unsigned int, so the following error path check will always be false, even when "spi-max-frequency" property is invalid/missing: priv->max_hz = fdtdec_get_int(blob, node, "spi-max-frequency", -1); if (priv->max_hz < 0) { ... } Replace the fdtdec call with dev_read_u32_default() and use 0 as the default value. Error out if max_hz is zero. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com>
* Merge tag 'xilinx-for-v2021.04' of ↵Tom Rini2021-01-061-4/+2
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze into next Xilinx changes for v2021.04 arm64: - DT updates microblaze: - Add support for NOR device support spi: - Fix unaligned data write issue nand: - Minor code change xilinx: - Fru fix in limit calculation - Fill git repo link for all Xilinx boards video: - Add support for seps525 spi display tools: - Minor Vitis file support cmd/common - Minor code indentation fixes serial: - Uartlite debug uart initialization fix
| * spi: zynqmp_gqspi: Fix unaligned data writes issueT Karthik Reddy2021-01-041-4/+2
| | | | | | | | | | | | | | | | | | When unaligned 3 bytes data write operation is performed, 3rd byte is being over written by 1st byte of 3 bytes data. This patch fixes it. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-0523-61/+63
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * | dm: Rename U_BOOT_DRIVER_ALIAS to DM_DRIVER_ALIASSimon Glass2021-01-052-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We use the U_BOOT_ prefix (i.e. U_BOOT_DRIVER) to declare a driver but in every other case we just use DM_. Update the alias macros to use the DM_ prefix. We could perhaps rename U_BOOT_DRIVER() to DM_DRIVER(), but this macro is widely used and there is at least some benefit to indicating it us a U-Boot driver, particularly for code ported from Linux. So for now, let's keep that name. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Access device ofnode through functionsSimon Glass2021-01-051-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: core: Use dev_has_ofnode() instead of dev_of_valid()Simon Glass2021-01-051-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have two functions which do the same thing. Standardise on dev_has_ofnode() since there is no such thing as an 'invalid' ofnode in normal operation: it is either null or missing. Also move the functions into one place. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
| * | x86: spl: Move priv/plat structs to headersSimon Glass2021-01-052-11/+11
| | | | | | | | | | | | | | | | | | | | | With the new of-platdata, these need to be available to dt_platdata.c so must be in header files. Move them. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | dm: Use access methods for dev/uclass private dataSimon Glass2021-01-0520-45/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Most drivers use these access methods but a few do not. Update them. In some cases the access is not permitted, so mark those with a FIXME tag for the maintainer to check. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Acked-by: Pratyush Yadav <p.yadav@ti.com>
* | | Merge tag 'v2021.01-rc5' into nextTom Rini2021-01-055-117/+922
|\ \ \ | |/ / |/| / | |/ | | | | Prepare v2021.01-rc5 Signed-off-by: Tom Rini <trini@konsulko.com>
| * spi: ca_sflash: Add CAxxxx SPI Flash ControllerPengpeng Chen2020-12-183-0/+585
| | | | | | | | | | | | | | | | | | | | | | | | | | Add SPI Flash controller driver for Cortina Access CAxxxx SoCs Signed-off-by: Pengpeng Chen <pengpeng.chen@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Vignesh R <vigneshr@ti.com> CC: Tom Rini <trini@konsulko.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: dw: Add mem_opsSean Anderson2020-12-181-7/+111
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The designware ssi device has "broken" chip select behaviour [1], and needs specific manipulation to use the built-in chip select. The existing fix is to use an external GPIO for chip select, but typically the K210 has SPI3 directly connected to a flash chip with dedicated pins. This makes it impossible to use the spi_xfer function to use spi, since the CS is de-asserted in between calls. This patch adds an implementation of exec_op, which gives correct behaviour when reading/writing spi flash. This patch also rearranges the headers to conform to U-Boot style. [1] https://lkml.org/lkml/2015/12/23/132 Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: dw: Add support for multiple CTRLR0 layoutsSean Anderson2020-12-181-35/+149
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | CTRLR0 can have several different layouts depending on the specific device (dw-apb-ssi vs dwc-ssi), and specific parameters set during synthesis. Update the driver to support three specific configurations: dw-apb-ssi with SSI_MAX_XFER_SIZE=16, dw-apb-ssi with SSI_MAX_XFER_SIZE=32, and dwc-ssi. dw-apb-ssi is the version of the device on Altera/Intel SoCFPGAs, MSCC SoCs, and Canaan Kendryte K210 SoCs. This is the only version this driver supported before this change. The register layout before version 3.23a is: | 31 .. 16 | | other stuff | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | DFS | Note that DFS (Data Frame Size) is only 4 bits, limiting transfers to data frames of 16 bits or less. In version 3.23a, the SSI_MAX_XFER_SIZE parameter was introduced. This parameter defaults to 16 (resulting in the same layout as prior versions), but may also be set to 32. To allow setting longer data frame sizes, a new DFS_32 register was introduced: | 31 .. 21 | 20 .. 16 | | other stuff | DFS_32 | | 15 .. 10 | 9 .. 8 | 7 .. 6 | 5 .. 4 | 3 .. 0 | | other stuff | TMOD | MODE | FRF | all zeros | The old DFS field no longer controls the data frame size. To detect this layout, we try writing 0xF to DFS. If we read back 0x0, then this device has SSI_MAX_XFER_SIZE=32. dwc-ssi is the version of the device on Intel Keem Bay SoCs and Canaan Kendryte K210 SoCs. The layout of ctrlr0 is: | 31 .. 16 | | other stuff | | 15 .. 12 | 11 .. 10 | 9 .. 8 | 7 .. 6 | 4 .. 0 | | other stuff | TMOD | MODE | FRF | DFS_32 | The semantics of the fields have not changed since the previous version. However, SSI_MAX_XFER_SIZE is effectively always 32. To support these different layouts, we model our approach on the one which the Linux kernel has taken. During probe, the driver calls an init function stored in driver_data. This init function is responsible for determining the layout of CTRLR0, and supplying the update_cr0 function. The style of and information behind this commit is based on the Linux MMIO driver for these devices. Specific reference was made to the series adding support for Intel Keem Bay SoCs [1]. [1] https://lore.kernel.org/linux-spi/20200505130618.554-1-wan.ahmad.zainie.wan.mohamad@intel.com/ Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: dw: Rearrange struct dw_spi_privSean Anderson2020-12-181-14/+13
| | | | | | | | | | | | | | | | | | This should reduce the size of the struct, and also groups more similar fields together. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: dw: Remove spi_enable_chipSean Anderson2020-12-181-11/+6
| | | | | | | | | | | | | | This function does nothing but wrap dw_write. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: dw: Rename registers to match datasheetSean Anderson2020-12-181-9/+9
| | | | | | | | | | | | | | A few registers had slightly different names from what is in the datasheet. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: dw: Use generic function to read reg addressSean Anderson2020-12-181-0/+2
| | | | | | | | | | | | | | | | | | Using an fdt-specific function causes problems when compiled with a live tree. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: dw: Rename "cs-gpio" to "cs-gpios"Sean Anderson2020-12-181-1/+2
| | | | | | | | | | | | | | | | | | This property is named differently than other SPI drivers with the same property, as well as the property as used in Linux. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: dw: Convert calls to debug to dev_*Sean Anderson2020-12-181-19/+19
| | | | | | | | | | | | | | | | | | | | | | This allows different log levels to be enabled or disabled depending on the desired level of verbosity. In particular, it allows for general debug information to be printed while excluding more verbose logging which may interfere with timing. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: dw: Fix driving MOSI low while recievingSean Anderson2020-12-181-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The resting state of MOSI is high when nothing is driving it. If we drive it low while recieving, it looks like we are transmitting 0x00 instead of transmitting nothing. This can confuse slaves (like SD cards) which allow new commands to be sent over MOSI while they are returning data over MISO. The return of MOSI from 0 to 1 at the end of recieving a byte can look like a start bit and a transmission bit to an SD card. This will cause the card to become out-of-sync with the SPI device, as it thinks the device has already started transmitting two bytes of a new command. The mmc-spi driver will not detect the R1 response from the SD card, since it is sent too early, and offset by two bits. This patch fixes transfer errors when using SD cards with dw spi. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: migrate trace to dev and log macro in spi uclassPatrick Delaunay2020-12-181-23/+28
| | | | | | | | | | | | | | | | | | | | | | | | Define LOG_CATEGORY and change printf and pr_* to dev_ (when dev is available) or log_ macro. This patch adds the support of logging feature with log command (filtering, display of device name in trace) and allows to suppress traces via the syslog driver. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
generated by cgit (git 2.34.1) at 2025-09-22 14:07:13 +0000