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* spi: atcspi200: Change include orderJagan Teki2019-05-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | Like clk_get_by_index, there is requirement for clk_get_by_index_nodev. In this case to make common code functionalities for dev and nodev, clk_get_by_index is trying to get the index of clock by passing ofnode instead of actual dev like current gpio uclass does. In these scenarios with current order of include files the atcspi200_spi driver is unable to find CONFIG_ENV_SIZE. In file included from arch/nds32/include/asm/u-boot.h:24, from include/dm/of.h:10, from include/dm/ofnode.h:12, from include/clk.h:11, from drivers/spi/atcspi200_spi.c:9: include/environment.h:145:19: error: 'CONFIG_ENV_SIZE' undeclared here (not in a function); did you mean 'CONFIG_CMD_XIMG'? #define ENV_SIZE (CONFIG_ENV_SIZE - ENV_HEADER_SIZE) So, fix consists of changing the order of include files in atcspi200_spi.c to include first common.h file. Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2019-04-173-258/+108
|\ | | | | | | | | - drop non-DM code from ti_qspi - support spi-mem for ti_qspi
| * spi: ti_qspi: Convert to spi-mem opsVignesh Raghavendra2019-04-171-64/+68
| | | | | | | | | | | | | | | | | | Convert driver to use spi-mem ops in order to support accelerated MMIO flash interface in generic way and for better performance. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: ti_qspi: Drop non DM codeVignesh Raghavendra2019-04-173-200/+46
| | | | | | | | | | | | | | | | | | | | | | Now that all boards using TI QSPI have moved to DM and DT, drop non DM code completely. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com> [jagan: update MIGRATION.txt, rebase config_whitelist.txt] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | spi: zynqmp_gqspi: Fix tap delay values at 100MHz and 150MHzSiva Durga Prasad Paladugu2019-04-161-2/+2
|/ | | | | | | | This patch fixes the tap delay values to be set at 100MHz and 150MHz as per TRM by fixing the if condition to use <= instead of <. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2019-04-146-9/+38
|\ | | | | | | | | | | | | | | | | Conflicts: arch/arm/dts/armada-385-amc.dts arch/arm/dts/armada-xp-theadorable.dts arch/arm/dts/stm32mp157c-ev1-u-boot.dtsi Signed-off-by: Tom Rini <trini@konsulko.com>
| * dm: spi: Read default speed and mode values from DTPatrick Delaunay2019-04-121-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch update the behavior introduced by commit 96907c0fe50a ("dm: spi: Read default speed and mode values from DT") In case of DT boot, don't read default speed and mode for SPI from CONFIG_* but instead read from DT node. This will make sure that boards with multiple SPI/QSPI controllers can be probed at different bus frequencies and SPI modes. Remove also use in boards of the value speed=0 (no more supported) for ENV in SPI by using CONFIG_ENV_SPI_MAX_HZ=0. DT values will be always used when available (full DM support of SPI slave with available DT node) even if speed and mode are requested; for example in splash screen support (in splash_sf_read_raw) or in SPL boot (in spl_spi_load_image). The caller of spi_get_bus_and_cs() no more need to force speed=0. But the current behavior don't change if the SPI slave is not present (device with generic driver is created automatically) or if platdata is used (CONFIG_OF_PLATDATA). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: fsl_dspi fix to stop extra transmissionsJared Bents2019-04-121-4/+26
| | | | | | | | | | | | | | | | | | | | Update to prevent a byte of zeros being transmitted between each byte in the tx buffer when providing both a tx buffer and a rx buffer. Signed-off-by: Jared Bents <jared.bents@rockwellcollins.com> Cc: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com> Acked-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: spi-mem: Check if exec_op function is set before calling itBernhard Messerklinger2019-04-121-1/+1
| | | | | | | | | | | | | | | | | | | | Add check if exec_op is set before calling it. At the moment it is called unconditionally, which leads to a crash if it is not set correctly. Signed-off-by: Bernhard Messerklinger <bernhard.messerklinger@br-automation.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: cadence_qspi: Add quad write supportLey Foon Tan2019-04-123-3/+8
| | | | | | | | | | | | | | | | | | | | Use quad write if SPI_TX_QUAD flag is set. Tested quad write on Stratix 10 SoC board (Micron serial NOR flash, mt25qu02g) Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* | spi: stm32_qspi: move to exec_opChristophe Kerello2019-04-122-383/+245
|/ | | | | | | | | | | | | | | | | | | | We are facing issues in the driver since SPI NOR framework has moved on SPI MEM framework, and SPI NAND framework is not running properly with the current driver. To be able to solve issues met on SPI NOR Flashes and to be able to support SPI NAND Flashes, the driver has been reworked. We are now using exec_op ops instead of using xfer ops. Thanks to this rework, the driver has been successfully tested with: - mx66l51235l SPI NOR Flash on stm32f746 SOC - n25q128a SPI NOR Flash on stm32f769 SOC - mx66l51235l SPI NOR Flash on stm32mp1 SOC - mt29f2g01abagd SPI NAND Flash on stm32mp1 SOC Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Tested-by: Patrick DELAUNAY <patrick.delaunay@st.com> Reviewed-by: Patrick DELAUNAY <patrick.delaunay@st.com>
* spi: Rename sun4i_spi.c into spi-sunxi.cJagan Teki2019-03-043-6/+8
| | | | | | | | | | | Now the same SPI controller driver is reusable in all Allwinner SoC variants, so rename the existing sun4i_spi.c into spi-sunxi.c which eventually look like a common sunxi driver. Also update the function, variable, structure names in driver from sun4i into sunxi. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* spi: sun4i: Driver cleanupJagan Teki2019-03-041-110/+80
| | | | | | | | | | - drop unused macros. - use base instead of base_addr, for better code readability - move .probe and .ofdata_to_platdata functions in required places to add platdata support in future. - use sentinel sun4i_spi_ids. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* spi: sun4: Add A31 spi controller supportJagan Teki2019-03-042-3/+102
| | | | | | | | | | | The usual SPI transmission protocol in Allwinner A10 and A31 controllers share similar context with minimal changes in register offsets along with few additional register bits on A31. So, add A31 spi controller support in existing sun4i_spi with A31 specific register offsets and bits. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* spi: sun4i: Add CLK supportJagan Teki2019-03-041-8/+48
| | | | | | | | | | | | | | | | | Add CLK support to enable AHB and MOD SPI clocks on sun4i_spi driver. Clock disablement could be done while releasing the bus transfer, but the existing code doesn't disable the clocks it only taken care of clock enablement globally in probe. So to make a proper clock handling, the clocks should enable it in claim and disable it in release. This patch would also do that change, by enable and disable clock in proper order. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* spi: sun4i: Support fifo_depth via drvdataJagan Teki2019-03-041-3/+3
| | | | | | | | | Support fifo_depth via drvdata instead of macro definition, this would eventually reduce another macro definition for new SPI controller fifo depth support addition. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* spi: sun4i: Access registers and bits via enum offsetsJagan Teki2019-03-041-42/+112
| | | | | | | | | | | | | | | | Allwinner support two different SPI controllers one for A10 and another for A31 with minimal changes in register offsets and respective register bits, but the logic for accessing the SPI master via SPI slave remains nearly similar. Add enum offsets for register set and register bits, so-that it can access both classes of SPI controllers. Assign same control register for global, transfer and fifo control registers to make the same code compatible with A31 SPI controller. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Stefan Mavrodiev <stefan@olimex.com> # A20-SOM204
* spi: sun4i: Simplify reg writes using set/clrbits_le32Jagan Teki2019-03-041-13/+8
| | | | | | | Update the existing register writes using setbits_le32 and clrbits_le32 in required places. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* spi: sun4i: Poll for rxfifo to be filled upJagan Teki2019-03-041-6/+9
| | | | | | | | | | | | | | | To drain rx fifo the fifo need to poll for how much data has been filled up in rx fifo. To achieve this, the current code is using wait_for_bit logic on control register with exchange burst mode mask, which is not a proper way of waiting for fifo filled up. So, add code for polling rxfifo to be filled up using fifo status register. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Andre Przywara <andre.przywara@arm.com>
* spi: designware: Change include orderHoratiu.Vultur@microchip.com2019-03-041-1/+1
| | | | | | | | | | | | | | | | With current order of include files, the file designware_spi.c can't see that the struct global_data has the member board_type when CONFIG_BOARD_TYPES is defined. By not seeing this then all the members are shifted in the struct global_data. So when the driver is trying to read from device tree blob, it would pass the wrong address to the function 'fdtdev_get_int'. This will make to use the default frequency 500000. The fix consists of changing the order of include files in designware_spi.c to include first common.h file. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com>
* spi: omap3: fix set_wordlen() reading from incorrect address for CHCONFDavid Rivshin2019-02-281-1/+1
| | | | | | | | | | | | _omap3_spi_set_wordlen() indexed the regs->channel[] array with the old wordlen (instead of the chipselect number) when reading the current CHCONF register value. This meant it read from the wrong memory location, modified that value, and then wrote it back to the correct CHCONF register. The end result is that most slave configuration settings would be lost, such as clock divisor, clock/chipselect polarities, etc. Fixes: 77b8d04854f4 ("spi: omap3: Convert to driver model") Signed-off-by: David Rivshin <drivshin@allworx.com>
* spi: zynqmp_gqspi: Enable versal compatible stringMichal Simek2019-02-141-0/+1
| | | | | | Trivial patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* configs: Don't use SPI_FLASH_BAR as defaultVignesh R2019-02-071-0/+6
| | | | | | | | | | | | | | | Now that new SPI NOR layer uses stateless 4 byte opcodes by default, don't enable SPI_FLASH_BAR. For SPI controllers that cannot support 4-byte addressing, (stm32_qspi.c, fsl_qspi.c, mtk_qspi.c, ich.c, renesas_rpc_spi.c) add an imply clause to enable SPI_FLASH_BAR so as to not break functionality. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* mtd: spi: Switch to new SPI NOR frameworkVignesh R2019-02-071-2/+2
| | | | | | | | | | | | | Switch spi_flash_* interfaces to call into new SPI NOR framework via MTD layer. Fix up sf_dataflash to work in legacy way. And update sandbox to use new interfaces/definitions Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* spi: Add non DM version of SPI_MEMVignesh R2019-02-073-2/+108
| | | | | | | | | | | | Add non DM version of SPI_MEM to support easy migration to new SPI NOR framework. This can be removed once DM_SPI conversion is complete. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* spi: spi-mem: Claim SPI bus before spi mem accessVignesh R2019-02-071-5/+8
| | | | | | | | | | | | | | It is necessary to call spi_claim_bus() before starting any SPI transactions and this restriction would also apply when calling spi-mem operations. Therefore claim and release bus before requesting transfer via exec_op. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* spi: spi-mem: Extend spi_mem_adjust_op_size() to honor max xfer sizeVignesh R2019-02-071-0/+19
| | | | | | | | | | | | Extend spi_mem_adjust_op_size() to take spi->max_write_size and spi->max_read_size into account. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* spi: spi-mem: Allow use of spi_mem_exec_op for all SPI modesVignesh R2019-02-071-9/+0
| | | | | | | | | | | | SPI controllers support all types of SPI modes including dual/quad bus widths. Therefore remove constraint wrt SPI mode from spi-mem layer. Signed-off-by: Vignesh R <vigneshr@ti.com> Tested-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Tested-by: Stefan Roese <sr@denx.de> Tested-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com> #zynq-microzed
* spi: mxc_spi: Fix build warning on ARM64 platformsYe Li2019-01-281-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When building mxc_spi driver on ARM64 platforms, get below build warnings. Fix it in this patch. In file included from include/common.h:48:0, from drivers/spi/mxc_spi.c:9: drivers/spi/mxc_spi.c: In function ‘spi_xchg_single’: drivers/spi/mxc_spi.c:232:21: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ drivers/spi/mxc_spi.c:232:32: warning: cast from pointer to integer of different size [-Wpointer-to-int-cast] _func_, bitlen, (u32)dout, (u32)din); ^ include/log.h:135:26: note: in definition of macro ‘debug_cond’ printf(pr_fmt(fmt), ##args); \ ^~~~ drivers/spi/mxc_spi.c:231:2: note: in expansion of macro ‘debug’ debug("%s: bitlen %d dout 0x%x din 0x%x\n", ^~~~~ Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* mips: spi: mscc: Add fast bitbang SPI driverLars Povlsen2019-01-163-0/+244
| | | | | | | | | | This patch add a new SPI driver for MSCC SOCs that does not sport the designware SPI hardware controller. Performance gain: 7.664 seconds vs. 17.633 for 1 Mbyte write. Signed-off-by: Lars Povlsen <lars.povlsen@microchip.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* spi: sun4i: Add rx_buf NULL pointer checkStefan Mavrodiev2019-01-021-1/+2
| | | | | | | | | | | | | Current driver doesn't check if the destination pointer is NULL. This cause the data from the FIFO to be stored inside the internal SDRAM ( address 0 ). The patch add simple check if the destination pointer is NULL. Signed-off-by: Stefan Mavrodiev <stefan@olimex.com> Acked-by: Jagan Teki <jagan@openedev.com> [jagan: fix commit message] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* DW SPI: Allow to overload the management of the external CSGregory CLEMENT2018-12-191-1/+7
| | | | | | | | | | | | On some platforms, as the Ocelot ones, when wanting to control the CS through software, it is not possible to do it through the GPIO controller. Indeed, this signal is managed through a dedicated range of registers inside the SoC.. By declaring the external_cs_manage function as weak, it is possible to manage the CS at platform level and then using the appropriate registers. Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2018-12-0516-98/+723
|\ | | | | | | | | | | | | | | - Various MTD fixes from Boris - Zap various unused / legacy paths. - pxa3xx NAND update from Miquel Signed-off-by: Tom Rini <trini@konsulko.com>
| * spi: mpc8xx: Migrate to DM_SPIChristophe Leroy2018-11-272-155/+36
| | | | | | | | | | | | | | | | Drop non-dm code and migrate into DM_SPI. Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> [jagan: Move config menu in DM_SPI area] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: Remove unused spi_initJagan Teki2018-11-2711-58/+0
| | | | | | | | | | | | | | Remove spi_init definition which never used on respective code since from many years. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * dm: platform_data: spi: s/pl022_spi.h/spi_pl022.hJagan Teki2018-11-271-1/+1
| | | | | | | | | | | | | | | | Rename platform_data include file as spi_pl022.h from pl022_spi.h, this is generic notation used for spi platdata include files. Acked-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: pl022: Drop unnecessary include filesJagan Teki2018-11-271-5/+0
| | | | | | | | | | | | | | | | This patch can drop unnecessary include files in pl022_spi driver. Acked-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: pl022: Simplify platdata codeJagan Teki2018-11-271-28/+20
| | | | | | | | | | | | | | | | | | | | | | pl022 spi driver support both OF_CONTROL and PLATDATA, this patch is trying to simplify the code that differentiating platdata vs of_control. - Move OF_CONTROL code at one place - Handle clock setup code directly in pl022_spi_ofdata_to_platdata Acked-by: Quentin Schulz <quentin.schulz@bootlin.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
| * spi: mtk_qspi: add qspi driver for MT7629 SoCGuochun Mao2018-11-243-0/+367
| | | | | | | | | | | | | | | | This patch adds MT7629 qspi driver for accessing SPI NOR flash. Signed-off-by: Guochun Mao <guochun.mao@mediatek.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Jagan Teki <jagan@openedev.com>
| * spi: Add Amlogic Meson SPI Flash Controller driverNeil Armstrong2018-11-243-0/+329
| | | | | | | | | | | | | | | | | | | | The Amlogic Meson SoCs embeds a Flash oriented SPI Controller name SPIFC. This driver, ported from the Linux meson-spi-spifc driver, add support for this controller on the Amlogic Meson GX SoCs in U-Boot. Tested-by: Jerome Brunet <jbrunet@baylibre.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* | spi, mpc8xx: migrate to DM_SPIChristophe Leroy2018-12-031-149/+30
| | | | | | | | Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
* | spi: cadence_qspi: use "cdns,qspi-nor" as compatibleSimon Goldschmidt2018-11-291-1/+1
| | | | | | | | | | | | | | Linux uses "cdns,qspi-nor" as compatible string for the cadence qspi driver, so change driver, docs and all device trees. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* | dm: spi: prevent setting a speed of 0 HzSimon Goldschmidt2018-11-201-3/+12
|/ | | | | | | | | | | | | | When the device tree is missing a correct spi slave description below the bus (compatible "spi-flash" or spi-max-frequency are missing), the 'set_speed' callback can be called with 'speed' == 0 Hz. At least with cadence qspi, this leads to a division by zero. Prevent this by initializing speed to 100 kHz in this case (same fallback value as is done in 'dm_spi_claim_bus') and issue a warning to console. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek2018-10-161-2/+2
| | | | | | | | | | | | | | | | | | Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2018-10-121-19/+28
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| * spi: davinci: Add platdata supportJagan Teki2018-10-101-19/+28
| | | | | | | | | | | | | | | | | | Davanci spi driver has DM support already, this patch add support for platdata so-that SPL can use it for low foot-print. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Adam Ford <aford173@gmail.com>
* | dm: spi: Add logging of some return valuesSimon Glass2018-10-091-3/+3
| | | | | | | | | | | | | | | | When SPI flash operations fail it is helpful to be able to see the error codes and where they are generated. Add logging to capture this information for read operations. Signed-off-by: Simon Glass <sjg@chromium.org>
* | sandbox: spi: Add more loggingSimon Glass2018-10-091-29/+9
|/ | | | | | | Add logging to aid debugging features in these drivers. Also drop some code in sandbox_spi_xfer() which is not used. Signed-off-by: Simon Glass <sjg@chromium.org>
* spi: Add SPI driver for MT76xx SoCsStefan Roese2018-10-043-0/+321
| | | | | | | | | | | | | | | | | | This patch adds the SPI driver for the MediaTek MT7688 SoC (and derivates). Its been tested on the LinkIt Smart 7688 and the Gardena Smart Gateway with and SPI NOR on CS0 and on the Gardena Smart Gateway additionally with an SPI NAND on CS1. Note that the SPI controller only supports a max transfer size of 32 bytes. This driver implementes a workaround to enable bigger xfer sizes to speed up the transfer especially for the SPI NAND support. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Jagan Teki <jagan@openedev.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Cc: Piotr Dymacz <pepe2k@gmail.com> Reviewed-by: Jagan Teki <jagan@openedev.com> Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-spiTom Rini2018-10-026-203/+702
|\ | | | | | | | | | | | | This is the PR for SPI-NAND changes along with few spi changes. [trini: Re-sync changes for ls1012afrwy_qspi*_defconfig] Signed-off-by: Tom Rini <trini@konsulko.com>
generated by cgit (git 2.34.1) at 2024-11-19 18:37:32 +0000