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* common: Drop asm/global_data.h from common headerSimon Glass2021-02-021-0/+1
| | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-136-27/+22
| | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-136-12/+12
| | | | | | | This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2020-12-136-23/+23
| | | | | | Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-136-6/+6
| | | | | | | | | | We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-139-16/+16
| | | | | | | | | | | | This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* ram: rockchip: px30: add a config-based ddr selectionHeiko Stuebner2020-10-302-0/+29
| | | | | | | | | | | | | | | The SRAM on the PX30 is not big enough to hold multiple DDR configs so it needs to be selected during build. So far simply the DDR3 config was always selected and getting DDR4 or LPDDR2/3 initialized would require a code modification. So add Kconfig options similar to RK3399 to allow selecting the DDR4 and LPDDR2/3 options instead, while DDR3 stays the default as before. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* rockchip: ram: fix debug funcfion define when RAM_ROCKCHIP_DEBUG not setKever Yang2020-07-221-0/+13
| | | | | | | | The empty function define should not be in the header file, or else the build will error with function multi definition after CONFIG_RAM_ROCKCHIP_DEBUG is disabled. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Mark existing prints via RAM_ROCKCHIP_DEBUGJagan Teki2020-07-221-4/+8
| | | | | | | | | | | | | | Right now all these debug statements are printing on the console to make sure proper dram initialization happens.   Mark them into RAM_ROCKCHIP_DEBUG would be more meaningful and work like before since the RAM_ROCKCHIP_DEBUG is by default yet. No functionality changes. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Drop debug stride in driverJagan Teki2020-07-221-25/+0
| | | | | | | | | | stride debug is already present in sdram_common.c via RAM_ROCKCHIP_DEBUG. So, drop the redundant debug stride code in rk3399 driver. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* dtoc: extend dtoc to use struct driver_info when linking nodesWalter Lozano2020-07-091-1/+1
| | | | | | | | | | | | | | | | In the current implementation, when dtoc parses a dtb to generate a struct platdata it converts the information related to linked nodes as pointers to struct platdata of destination nodes. By doing this, it makes difficult to get pointer to udevices created based on these information. This patch extends dtoc to use struct driver_info when populating information about linked nodes, which makes it easier to later get the devices created. In this context, reimplement functions like clk_get_by_index_platdata() which made use of the previous approach. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* drivers: rename drivers to match compatible stringWalter Lozano2020-07-094-4/+4
| | | | | | | | | | | | | | | | | When using OF_PLATDATA, the bind process between devices and drivers is performed trying to match compatible string with driver names. However driver names are not strictly defined, and also there are different names used when declaring a driver with U_BOOT_DRIVER, the name of the symbol used in the linker list and the used in the struct driver_info. In order to make things a bit more clear, rename the drivers names. This will also help for further OF_PLATDATA improvements, such as checking for valid driver names. Signed-off-by: Walter Lozano <walter.lozano@collabora.com> Reviewed-by: Simon Glass <sjg@chromium.org> Add a fix for sandbox of-platdata to avoid using an invalid ANSI colour: Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-189-0/+9
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-187-0/+7
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop init.h from common headerSimon Glass2020-05-186-0/+6
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* ram: rockchip: Fix Kconfig dependency for RAM_ROCKCHIP_DEBUGMichal Simek2020-02-131-0/+1
| | | | | | | | | | | | | There is no reason to show RAM_ROCKCHIP_DEBUG entry in other .config files as I see it for Xilinx ZynqMP. \# CONFIG_U_QE is not set \# CONFIG_RAM is not set CONFIG_RAM_ROCKCHIP_DEBUG=y Add missing dependency on RAM_ROCKCHIP driver. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* dm: core: Require users of devres to include the headerSimon Glass2020-02-051-0/+1
| | | | | | | | | | At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
* ram: rk3328: only do data traning for cs0Kever Yang2020-01-301-7/+3
| | | | | | | | | No need to do twice data training for rk3328 ddr sdram, we re-use the setting for both channel. And adjust the sdram_init properly for correct init flow. Signed-off-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: YouMin Chen <cym@rock-chips.com>
* arm: rockchip: Add common cru.hJagan Teki2020-01-302-10/+10
| | | | | | | | | | | | | | | | | Few of the rockchip family SoC atleast rk3288, rk3399 are sharing some cru register bits so adding common code between these SoC families would require to include both cru include files that indeed resulting function declarations error. So, create a common cru include as cru.h then include the rk3399 arch cru include file and move the common cru register bit definitions into it. The rest of rockchip cru files will add it in future. Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
* ram: rk3399: don't assume phy_io_config() uses real regsThomas Hebb2020-01-301-4/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | In the RK3399 DRAM driver, the function set_ds_odt() supports operating in two different modes, selected by the ctl_phy_reg argument: when true, the function reads and writes directly from the DRAM registers, accessed through "chan->pctl->denali_*"; when false, the function reads and writes from an array, accessed through "params->pctl_regs.denali_*", which is written to DRAM registers at a later time. However, phy_config_io(), which is called by set_ds_odt() to do a subset of its register operations, operates directly on DRAM registers at all times. This means that it reads incorrect values (and writes new values prematurely) when ctl_phy_reg in set_ds_odt() is false. Fix this by passing in the address of the registers to work with. This prevents an "Invalid DRV value" error in the SPL debug log and (presumably) results in a more correct end state. See the following logs from a RK3399 NanoPi M4 board (4GB LPDDR3): Before: sdram_init() Starting SDRAM initialization... phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 0 phy_io_config() Invalid DRV value. phy_io_config() Invalid DRV value. sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... After: sdram_init() Starting SDRAM initialization... sdram_init() sdram_init: data trained for rank 2, ch 0 sdram_init() sdram_init: data trained for rank 2, ch 1 Channel 0: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR3, 933MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride 256B stride sdram_init() Finish SDRAM initialization... Signed-off-by: Thomas Hebb <tommyhebb@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* common: Move hang() to the same header as panic()Simon Glass2020-01-173-0/+3
| | | | | | | | | | At present panic() is in the vsprintf.h header file. That does not seem like an obvious choice for hang(), even though it relates to panic(). So let's put hang() in its own header. Signed-off-by: Simon Glass <sjg@chromium.org> [trini: Migrate a few more files] Signed-off-by: Tom Rini <trini@konsulko.com>
* rockchip: rk3308: Add sdram driverAndy Yan2019-11-172-0/+56
| | | | | | | | A dm based dram driver for rk3308 u-boot to get capacity. Signed-off-by: Andy Yan <andy.yan@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Fix dram setting to make dram more stableYouMin Chen2019-11-171-21/+20
| | | | | | | | | | | | There are some code different with rockchip vendor code which may lead to different bugs, including: 1) Fix setting error about LPDDR3 dram size ODT. 2) Set phy io speed to 0x2. 3) Fix setting error about phy_pad_fdbk_drive. 4) Fix setting error about PI_WDQLVL_VREF_EN Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: update calculate_strideKever Yang2019-11-171-39/+119
| | | | | | | Update the calculation of the stride to support all the DRAM case. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Sync the io setting from Rockchip vendor codeKever Yang2019-11-171-30/+14
| | | | | | | | The io setting are updated after some bugfix in different rk3399 boards, sync the code from vendor. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: update lpddr4 timing for rk3399Kever Yang2019-11-172-9/+9
| | | | | | | | Update lpddr timing in lpddr4-400 and lpddr4-800 file from rockchip vendor code; Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: add support detect capacityYouMin Chen2019-11-171-21/+215
| | | | | | | | Add capacity detect for rk3399 so that the driver able to detect the capacity automatically. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: update the function of sdram_initYouMin Chen2019-11-171-123/+296
| | | | | | | Clean up the sdram_init to keep sync with rockchip source code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: fix error about get_ddrc0_con reg addrYouMin Chen2019-11-171-1/+1
| | | | | | | Correct the register to its correct name. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Clean up codeYouMin Chen2019-11-171-83/+93
| | | | | | | Clean up rk3399 dram driver source code for more readable. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: migrate to use common codeYouMin Chen2019-11-175-115/+118
| | | | | | | | For there are some structures and functions are common for all rockchip SoCs, migrate to use the common code so that we can clean up reduandent codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3328: use common sdram driverYouMin Chen2019-11-172-606/+159
| | | | | | | | RK3328 has a similar controller and phy with PX30, so we can use the common driver for it and remove the duplicate codes. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: px30: add sdram driverYouMin Chen2019-11-177-0/+1167
| | | | | | | | | | | | Add the sdram driver for PX30 to support ddr3, ddr4, lpddr2 and lpddr3. For TPL_BUILD, the driver implement full dram init and without DM support due to the limit of internal SRAM size. For SPL and U-Boot proper, it's a simple driver with dm for get dram_info like other SoCs. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: add phy driver code for PX30Kever Yang2019-11-171-0/+205
| | | | | | | | This sdram_phy_px30.c is based on PX30 SoC, the functions are common for phy, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: add controller code for PX30Kever Yang2019-11-171-0/+205
| | | | | | | | This sdram_pctl_px30.c is based on PX30 SoC, the functions are common for controller, other SoCs with similar hardware could re-use it. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: Default enable DRAM debug infoKever Yang2019-11-171-0/+1
| | | | | | | The debug info for dram is main about the capacity related info which is very important the board init, so set this default enable. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: move sdram_debug function into sdram_commonKever Yang2019-11-173-148/+144
| | | | | | | The functions for dram info print are part of common code. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: add common code for sdram driverKever Yang2019-11-173-0/+292
| | | | | | | | | There are some function like os_reg setting, capacity detect functions, can be used as common code for different Rockchip SoCs, add a sdram_common.c for all these functions. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: rename sdram_common.c/h to sdram.cKever Yang2019-11-178-8/+8
| | | | | | | | | | rename sdram_common.c in arch/arm/mach-rockchip to sdram.c; so that we can use the file name sdram_common.c in dram driver for better understand the code; clean the related file who has use the header file at the same time. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rockchip: rename sdram.h to sdram_rk3288.hKever Yang2019-11-173-3/+3
| | | | | | | | The header file sdram.h is used for rk3288 and similar SoCs, rename it to make it more understandable. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3328: Fix loading of skew valuesSimon South2019-11-101-1/+1
| | | | | | | | Fix a typo that caused incorrect values to be loaded into the DRAM controller's deskew registers. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3328: Use correct frequency units in functionSimon South2019-11-101-2/+2
| | | | | | | | | Fix a pair of tests in phy_dll_bypass_set() that used incorrect units for the DDR frequency, causing the DRAM controller to be misconfigured in most cases. Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3288: Initialize dram for TPL buildsJagan Teki2019-09-191-5/+10
| | | | | | | | | | | | | Few of the rk3288 boards like tinker, vyasa are using TPL, SPL bootchain so the dram initialization must needed during TPL stage. So add proper ifconstruct to satisfy both TPL, SPL and SPL-only bootchain boards. This eventually fixing TPL to SPL handoff, otherwise missing dram initilaztion at TPL stage would leads to SPL hang. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* ram: rk3399: update cap and ddrconfig for each channel after initKever Yang2019-08-231-78/+81
| | | | | | | | | We need to store all the ram related cap/map info back to register for each channel after all the init has been done in case some of register was reset during the process. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: ram: add full feature rk3328 DRAM driverKever Yang2019-08-051-3/+1015
| | | | | | | | | | This driver supports DDR3/LPDDR3/DDR4 SDRAM initialization. Signed-off-by: YouMin Chen <cym@rock-chips.com> Signed-off-by: Kever Yang <kever.yang@rock-chips.com> [cherry picked from commit https://github.com/rockchip-linux/u-boot/commit/9fb0777ec3cc6a89af9d2e0969c3bfe58306a88d with minor modifications] Signed-off-by: Matwey V. Kornilov <matwey.kornilov@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* rockchip: rk322x: sdram: use udelay instead of rockchip_udelayKever Yang2019-07-201-15/+14
| | | | | | | Use system api for udelay instead of vendor defined api, and rockchip_udelay() will be removed. Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Add lpddr4 set rate supportJagan Teki2019-07-201-12/+661
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Unlike rest of dram type chips, LPDDR4 initialization start with at board selected frequency (say 50MHz) and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. The lpddr4 set rate sequnce will follow by setting lpddr4 - dq out - ca odt - MR3 - MR12 - MR14 registers sets in sequential order. Here is sameple log about LPDDR4-100 init sequence in Rockpro64: Channel 0: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB Channel 1: LPDDR4, 50MHz BW=32 Col=10 Bk=8 CS0 Row=15 CS1 Row=15 CS=2 Die BW=16 Size=2048MB 256B stride channel 0 training pass channel 1 training pass change freq to 400 MHz 0, 1 channel 0 training pass channel 1 training pass change freq to 800 MHz 1, 0 This patch add support to this init sequence via lpddr4 set rate by taking sdram timing parameters from 400, 800 .inc files. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> (Fix travis error, use one ret instead of ret[2] in set_ctrl) Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
* ram: rk3399: Add set_rate sdram rk3399 opsJagan Teki2019-07-211-3/+8
| | | | | | | | | | | | | DDR set rate can be even required for lpddr4 and we need to keep the lpddr4 code to compile only for relevant boards which do support lpddr4. For this requirement, and for code readability handle data training via sdram_rk3399_ops with .set_rate and same will update in future while supporting lpddr4 code. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
* ram: rk3399: Add LPPDDR4-800 timings incJagan Teki2019-07-211-0/+1570
| | | | | | | | | | | | | | LPDDR4 initialization start with at board selected frequency and then it switches into 400MHz and 800MHz simultaneously to make the proper sequence work on each channel with associated training. So, add LPDDR4-800 timings inc file in driver area so-that these timings will take during LPDDR4 initialization phase. Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Signed-off-by: YouMin Chen <cym@rock-chips.com> Reviewed-by: Kever Yang <Kever.yang@rock-chips.com>
generated by cgit (git 2.34.1) at 2025-09-03 09:33:48 +0000