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* arm: a37xx: pci: Fix configuring PCIe resourcesPali Rohár2021-06-041-1/+157
| | | | | | | | | | | | | | | | | | | | | | | The `ranges` DT property of the PCIe node is currently ignored by Aardvark driver - all entries are used as transparent PCIe MEM, despite some of them being defined for IO in DT. This is because the driver does not setup PCIe outbound windows and thus a default configuration is used. This can cause an external abort on CPU when a device driver tries to access non-MEM space. Setup the PCIe windows according to the `ranges` property for all non-MEM resources (currently only IO) and also non-transparent MEM resources. Because Linux expects that bootloader does not setup Aardvark PCIe windows, disable them before booting Linux. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: a37xx: pci: Fix DT compatible string to Linux' DT compatiblePali Rohár2021-06-041-1/+1
| | | | | | | | | | Change DT compatible string for A3700 PCIe from 'marvell,armada-37xx-pcie' to 'marvell,armada-3700-pcie' to make U-Boot A3700 PCIe DT node compatible with Linux' DT node. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: a37xx: pci: Disable bus mastering when unloading driverPali Rohár2021-06-041-0/+6
| | | | | | | | | | | | | | | | | | Disable Root Bridge I/O space, memory space and bus mastering in Aardvark's remove method, which is called before booting Linux kernel. This ensures that PCIe device which was initialized and used by U-Boot cannot do new DMA transfers until Linux initializes PCI subsystem and loads appropriate drivers for the device. During initialization of PCI subsystem Linux in fact disables this bus mastering on Root Bridge (and later enables it when driver is loaded and configured), but there is a possibility of a small window after U-Boot boots Linux when bus mastering is enabled, which is not correct. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: a37xx: pci: Don't put link into LTSSM Recovery state during probePali Rohár2021-06-041-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During our debugging of the Aardvark driver in Linux we have discovered that the PCIE_CORE_LINK_CTRL_STAT_REG register in fact controls standard PCIe Link Control Register for PCIe Root Bridge. This led us to discover that the name of the PCIE_CORE_LINK_TRAINING macro and the corresponding comment by this macro's usage is misleading; this bit in fact controls Retrain Link, which, according to PCIe base spec is defined as: A write of 1b to this bit initiates Link retraining by directing the Physical Layer LTSSM to the Recovery state. If the LTSSM is already in Recovery or Configuration, re-entering Recovery is permitted but not required. Entering Recovery state is normally done from LTSSM L0, L0s and L1 states. But since the pci-aardvark.c driver enables Link Training just a few lines above, the controller is not in L0 ready state yet. So setting aardvark bit PCIE_CORE_LINK_TRAINING does not actually enter Recovery state at this place. Moreover, trying to enter LTSSM Recovery state without other configuration is causing issues for some cards (e.g. Atheros AR9xxx and QCA9xxx). Since Recovery state is not entered, these issues are not triggered. Remove code which tries to enter LTSSM Recovery state completely. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* drivers: pci: pcie_dw_common: fix Werror compilation errorGreen Wan2021-05-311-25/+29
| | | | | | | | Fix compilation error when Werror is turned on. The warning could possible break some CI builds. Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
* drivers: pci: add pcie support for fu740Green Wan2021-05-313-0/+518
| | | | | | | | | | | | | | Add pcie driver for SiFive fu740, the driver depends on fu740 gpio, clk and reset driver to do init. Force running at Gen1 for better capatible enumeration. Several devices are tested: a) M.2 NVMe SSD b) USB-to-PCI adapter c) Ethernet adapter (E1000 compatible) Signed-off-by: Green Wan <green.wan@sifive.com> Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
* pcie: designware: mvebu: do not configure ATU for IO when not usedMarcin Wojtas2021-05-161-12/+25
| | | | | | | | | | | | | The pcie_dw_mvebu configure ATU regions for memory, configuration and IO space types. However the latter is not obligatory and when not specified in the device tree, causes wrong ATU configuration. Fix that by adding a dependency on the detected PCIE regions count. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-on: https://sj1git1.cavium.com/18136 Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Tested-by: Kostya Porotchkin <kostap@marvell.com>
* pci: imx: disable imx6sdl LTSSM upon driver removeTim Harvey2021-05-021-1/+1
| | | | | | | | | | | | | | | | commit 6ecbe1375671 ("drivers: pci: imx: add imx_pcie_remove function") attempted to resolve an issue caused by MX6QDL not having a proper intneral PCIe core reset and thus hanging during kernel init if the bootloader had enabled PCI. The issue exists for IMX6Q, IMX6D, IXM6S, and IMX6DL. Fix the case for IMX6S and IMX6DL getting missed. This fixes IMX6S and IMX6DL with PCI enabled in U-Boot booting for Linux v4.11+. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@gmail.com>
* pci: pci-uclass: Add board_pci_fixup_dev for DM_PCITim Harvey2021-05-021-0/+6
| | | | | | | Add a board_pci_fixup_dev weak function to allow PCI device fixups during enumeration. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* pci: Update the highest subordinate bus number for bridge setupMasami Hiramatsu2021-05-021-0/+3
| | | | | | | | | | Update the highest subordinate bus number after probing the devices under the bus for setting up the bridge correctly. The commit 42f3663a3f67 ("pci: Update to use new sequence numbers") removed this but it is required if a PCIe bridge is under the bus. Fixes: 42f3663a3f67 ("pci: Update to use new sequence numbers") Signed-off-by: Masami Hiramatsu <masami.hiramatsu@linaro.org>
* arm: a37xx: pci: Fix processing PIO transfersPali Rohár2021-04-291-14/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trying to clear PIO_START register when it is non-zero (which indicates that previous PIO transfer has not finished yet) causes an External Abort with SError 0xbf000002. This bug is currently worked around in TF-A by handling External Aborts in EL3 and ignoring this particular SError. This workaround was also discussed at: https://git.trustedfirmware.org/TF-A/trusted-firmware-a.git/commit/?id=3c7dcdac5c50 https://lore.kernel.org/linux-pci/20190316161243.29517-1-repk@triplefau.lt/ https://lore.kernel.org/linux-pci/971be151d24312cc533989a64bd454b4@www.loen.fr/ https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/1541 Implement a proper fix to prevent this External Abort. As it is not possible to cancel a pending PIO transfer, simply do not start a new one if previous has not finished yet. In this case return an error to the caller. In most cases this SError happens when there is no PCIe card connected or when PCIe link is down. The reason is that in these cases a PIO transfer takes about 1.44 seconds. For this reason we also increase the wait timeout in pcie_advk_wait_pio() to 1.5 seconds. If PIO read transfer for PCI_VENDOR_ID register times out, or if it isn't possible to read it yet because previous transfer is not finished, return Completion Retry Status value instead of failing, to give the caller a chance to send a new read request. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* mips: octeon: Add Octeon PCIe host controller driverStefan Roese2021-04-283-0/+166
| | | | | | | | | | | | This patch adds the PCIe host controller driver for MIPS Octeon II/III. The driver mainly consist of the PCI config functions, as all of the complex serdes related port / lane setup, is done in the serdes / pcie code available in the "arch/mips/mach-octeon" directory. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* pci: add Amlogic Meson Designware PCIe controllerNeil Armstrong2021-04-153-0/+468
| | | | | | | | Add support for the DW PCIe controller found in the Amlogic Meson AXG and G12 (G12A, G12B, SM1) SoCs. This uses the common DW PCIe helpers introducted previously. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* pci: pcie_dw_rockchip: migrate to common Designware PCIe functionsNeil Armstrong2021-04-152-444/+30
| | | | | | Migrate the dw_rockchip driver to use the common DW PCIe helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* pci: pcie_dw_ti: migrate to common Designware PCIe functionsNeil Armstrong2021-04-152-408/+38
| | | | | | Migrate the dw_ti driver to use the common DW PCIe helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* pci: add common Designware PCIe functionsNeil Armstrong2021-04-154-0/+525
| | | | | | | | | | | | | | | With the introduction of pcie_dw_rockchip, and need to support the DW PCIe in the Amlogic AXG & G12 SoCs, most of the DW PCIe helpers would be duplicated. This introduce a "common" DW PCIe helpers file with common code merged from the dw_ti and dw_rockchip drivers and adapted to fit with the upcoming dw_meson. The following changes will switch the dw_ti and dw_rockchip to use these helpers. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Tested-by: Green Wan <green.wan@sifive.com> [bmeng: remove the blank line at EOF of drivers/pci/pcie_dw_common.c] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Mark 64bit Memory BARs as suchPhil Sutter2021-04-121-1/+2
| | | | | | | Just a bit more info to the reader. Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* Merge tag 'v2021.04-rc5' into nextTom Rini2021-03-292-2/+2
|\ | | | | | | Prepare v2021.04-rc5
| * pci: layerscape: Change to allocate zeroed memery for struct ls_pcieHou Zhiqiang2021-03-232-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | As on some incipient Layerscape platforms (LS1043A series) there isn't separate PF control register block, these registers reside in the LUT register block, so when the driver detected there isn't 'ctrl', it will assign the 'lut' address to the ls_pcie->ctrl. The current code allocate memory for the struct ls_pcie with random contents, this can result in skipping to assign the ls_pcie->ctrl with the 'lut' address, then further crash with the incorrect address. Fixes: 118e58e26eba ("pci: layerscape: Split the EP and RC driver") Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | video: Fix video on coreboot with the copy bufferSimon Glass2021-03-271-5/+2
|/ | | | | | | | | The copy buffer, if enabled, prevents booting from coreboot correctly, since no memory is allocated for it. Allow it to fall back to disabled in this situation. This ensures that a console is displayed, even if it is slow. Signed-off-by: Simon Glass <sjg@chromium.org>
* arm: a37xx: pci: Implement workaround for the readback value of VEND_IDPali Rohár2021-03-121-0/+10
| | | | | | | | | | | | | | | | | | | | Marvell Armada 3720 Functional Errata, Guidelines, and Restrictions document describes in erratum 4.1 PCIe value of vendor ID (Ref #: 243): The readback value of VEND_ID (RD0070000h [15:0]) is 1B4Bh, while it should read 11ABh. The firmware can write the correct value, 11ABh, through VEND_ID (RD0076044h [15:0]). Implement this workaround in U-Boot PCIe controller driver aardvark for both PCI vendor id and PCI subsystem vendor id. This change affects PCI vendor id of PCIe root bridge emulated by Linux kernel. With this change Linux kernel reports correct vendor id 11AB. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* pci: mpc85xx: Support 64-bit bus and cpu addressBin Meng2021-03-051-8/+8
| | | | | | | | | | | At present the driver only supports 32-bit bus and cpu address. The controller's outbound registers/fields for extended address are not programmed. Let's program them to support 64-bit bus and cpu address. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* pci: mpc85xx: Support controller register physical address beyond 32-bitBin Meng2021-03-051-3/+2
| | | | | | | | | | devfdt_get_addr_index() returns fdt_addr_t which might be a 64-bit physical address. Use map_physmem() to return the virtual address that can be used by a 32-bit machine. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* pci: mpc85xx: Wrap LAW programming with CONFIG_FSL_LAWBin Meng2021-03-051-0/+4
| | | | | | | | | | | For the QEMU ppce500 machine, LAW registers are not implemented hence CONFIG_FSL_LAW is not turned on and all LAW APIs are not available. We should wrap all LAW registers programming in the mpc85xx PCI driver with CONFIG_FSL_LAW. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heiko Schocher <hs@denx.de> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* pci: fsl_pci_init: Dynamically allocate the PCI regionsBin Meng2021-03-051-0/+5
| | | | | | | | | | | | | | | Commit e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions") changes 'struct pci_controller'.regions from pre-allocated array of regions to dynamically allocated, which unfortunately broken lots of boards that still use the non-DM PCI driver. This patch changes the non-DM fsl_pci_init driver to dynamically allocate the regions, just like what's done in the pci uclass driver. Fixes: e002474158d1 ("pci: pci-uclass: Dynamically allocate the PCI regions") Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* pci: pci_mvebu: set local dev to number 1Marek Behún2021-02-261-1/+1
| | | | | | | | | | | | | | | | | | | | | | Linux displays the real PCIe card connected to a mvebu PCIe slot as device 0, not 1. This is done by setting local dev number to 1, so that the local "Marvell Memory controller" device is on address 1. Let's do it also in U-Boot. With this commit the pci command in U-Boot prints something like: => pci Scanning PCI devices on bus 0 BusDevFun VendorId DeviceId Device Class Sub-Class _____________________________________________________________ 00.00.00 0x168c 0x003c Network controller 0x80 Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
* pci: pci_mvebu: refactor validation of addresses for config accessMarek Behún2021-02-261-28/+31
| | | | | | | | | | | | | | | | | | | | | | | | | Refactor validation of bdf parameter in mvebu_pcie_read/write_config functions. We can simplify the code by putting the validation into separate function. Also there are always only two devices visible on local bus: * on slot configured by function mvebu_pcie_set_local_dev_nr() (by default this register is set to 0) there is a "Marvell Memory controller", which isn't useful in root complex mode, * on all other slots the real PCIe card connected to the PCIe slot. We can simplify the code even more by simply allowing access only to the real PCIe card. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
* pci: pci_mvebu: debug rd/wr config as other drivers doMarek Behún2021-02-261-2/+2
| | | | | | | | | | | | Other drivers (aardvark, intel_fpga) print "(addr,size,val)" when debugging is enabled. Print size for pci_mvebu as well. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
* pci: pci_mvebu: cosmetic fixMarek Behún2021-02-261-3/+6
| | | | | | | | | | | Write bdf address in a same way in mvebu_pcie_read/write_config. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
* pci: pci_mvebu: use dev_seq instead of static variableMarek Behún2021-02-261-3/+1
| | | | | | | | | | | | | PCI uclass maps PCI bus numbers to the seq member of struct udevice. Use dev_seq(dev) as the bus number in mvebu_pcie_probe instead of an incrementing a static variable. Signed-off-by: Marek Behún <marek.behun@nic.cz> Cc: Stefan Roese <sr@denx.de> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc> Cc: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Stefan Roese <sr@denx.de>
* arm: a37xx: pci: Set Max Payload Size and Max Read Request Size to 512 bytesPali Rohár2021-02-261-0/+8
| | | | | | | | | | | | | | | Fix usage of VL805 XHCI PCIe controller when it is connected via PCIe to Armada 3720 SOC. Without this U-Boot crashes when trying to access enumerated USB devices connected to this XHCI PCIe controller. This should be done according to the PCIe Link Initialization sequence, as defined in Marvell Armada 3720 Functional Specification. Linux has this code too. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Marek Behún <marek.behun@nic.cz> Reviewed-by: Stefan Roese <sr@denx.de>
* pci: renesas: Fix BAR mapping on Gen3Marek Vasut2021-02-201-3/+3
| | | | | | | | | | Because the first PCIExAR(n) register is configured with the mapping, It is the second PCIExAR(n) register that must be written with 0, not the last one. Update the n from 4 to 1 to select the correct register. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pci: renesas: Make map address and mask power of two on Gen3Marek Vasut2021-02-201-3/+6
| | | | | | | | | Both the map address and mask must be power of two per documentation, adjust the code accordingly. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pci: renesas: Add root bus handling on Gen3Marek Vasut2021-02-201-1/+14
| | | | | | | | Add code to access the PCIe root bus space and configure it. Signed-off-by: Marek Vasut <marek.vasut+renesas@gmail.com> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* pci: pcie-brcmstb: Fix inbound window configurationsNicolas Saenz Julienne2021-02-181-7/+5
| | | | | | | | | | | | | | | | | | | So far we've assumed a fixed configuration for inbound windows as we had a single user for this controller. But the controller's DMA constraints were improved starting with BCM2711's B1 revision of the SoC, notably available in CM4 and Pi400. They allow for wider inbound windows. We can now cover the whole address space, whereas before we where limited to the lower 3GB. This information is passed to us through DT's 'dma-ranges' property and it's specially important for us to honor it since some interactions with the board's co-processor assume we're doing so (specifically the XHCI firmware load operation, which is handled by the co-processor after u-boot has correctly configured the PCIe controller). Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* pci: brcmstb: Cleanup controller state before handoverNicolas Saenz Julienne2021-02-181-0/+20
| | | | | | | | | | | | Make sure we handover the PCIe controller in a clean state. Some of the devices hanging from the PCIe bus might need to be properly reset through #PERST in order for Linux to be able to initialize them. This is specially important in order to properly initialize Raspberry Pi 4 B and 400's USB chip. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-1520-0/+20
|\ | | | | | | - Merge the patch to take <asm/global_data.h> out of <common.h>
| * common: Drop asm/global_data.h from common headerSimon Glass2021-02-0220-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | Merge git://git.denx.de/u-boot-marvellTom Rini2021-02-081-39/+27
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | - Espressobin: Set default env values at runtime (Pali) - Espressobin: Set the maximum slave SPI speed to 40MHz (Pali) - theadorable: PCIe test code enhancement and early deemphasis enabling (Stefan) - pci_mvebu: Disable config access to PCI host bridge ports (Stefan) - mv_sdhci: parse device-tree entry (Baruch)
| * | pci: pci_mvebu: Disable config access to PCI host bridge portsStefan Roese2021-02-081-39/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the PCI config routines in the Armada XP / 38x driver to not allow access to the PCIe root ports. While updating the Armada XP based theadorable to the latest mainline and testing it with the DM PCI driver I noticed, that the PCI root bridge was being configured incorrectly. Resulting in the PCIe Intel WiFi was not working correctly in Linux. With this patch applied, all PCIe devices work without any issues in Linux again. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Marek Behún <marek.behun@nic.cz> Cc: Phil Sutter <phil@nwl.cc> Cc: Mario Six <mario.six@gdsys.cc>
* | | pci: kconfig: layerscape: Change LX2162A PCIe node compatible stringHou Zhiqiang2021-02-081-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LX2162A is not like LX2160A which has different PCIe controller in rev1 and rev2 silicon. It supports only one configuration of PCIe controller, which is same as LS2088A. So update PCIe compatible string same as LS2088A. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Tested-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | | pci: layerscape: Remove the shadow SVR definitionsHou Zhiqiang2021-02-081-10/+2
|/ / | | | | | | | | | | | | | | | | | | This patch moves the SVR definitions to a new svr.h for Layerscape armv7 and armv8 platforms respectively, so that the PCIe driver can reuse them. Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Reviewed-by: Wasim Khan <wasim.khan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* / dm: pci: Correct use of wrong flag nameSimon Glass2021-02-031-1/+1
|/ | | | | | | Update a driver that uses the incorrect flag. Add a comment to hopefully prevent furture mistakes. Signed-off-by: Simon Glass <sjg@chromium.org>
* pci: Remove CONFIG_PCI_ENUM_ONLY as it's not used (any more)Stefan Roese2021-01-272-81/+41
| | | | | | | | | | | | | | This patch completely removes CONFIG_PCI_ENUM_ONLY from the PCI code as it is not configured for any board (any more). With this removal, some PCI related files get cleaned up a bit. Additional, dm_pciauto_setup_device() is now static, as it's not referenced from any code outside of this C file. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Simon Glass <sjg@chromium.org> Cc: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* arm64: a37xx: pci: Fix printing debug messagesPali Rohár2021-01-271-3/+2
| | | | | | | | | | | Value pcie->dev in function pcie_advk_probe() is not initialized yet so use dev as argument for dev_dbg()/dev_warn(). Function pcie_advk_wait_pio() itself prints error message on failure so do not print duplicate error message in caller. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* pci: pci_mvebu: Define an IO region as wellPhil Sutter2021-01-271-1/+27
| | | | | | | | | | Configure an IO region and window for PNP identical to how MEM region is set up. Linux does this only if the DT defines a pcie-io-aperture property for the SOC, but since all supported boards do this should not be needed. Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de>
* pci: Make auto-config code a little more robustPhil Sutter2021-01-271-4/+5
| | | | | | | | | | | | | | On my DS414, some PCI devices return odd values when probing BAR sizes. An obvious case is all-ones response, the Linux driver (drivers/pci/probe.c) catches those explicitly and a comment explains that either bit 0 or bit 1 must be clear (depending on MEM or IO type). Other BARs return e.g. 0xfff0000f or 0xfff00004 and thus manage to break size calculation due to the "middle" zeroes. Mitigate that copying more or less what Linux does and do a "find least bit set". Signed-off-by: Phil Sutter <phil@nwl.cc> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
* pci: Add Rockchip dwc based PCIe controller driverShawn Lin2021-01-213-0/+887
| | | | | | | | | Add Rockchip dwc based PCIe controller driver for rk356x platform. Driver support Gen3 by operating as a Root complex. Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang<kever.yang@rock-chips.com>
* common: board_r: Drop initr_pci wrapperOvidiu Panait2021-01-152-3/+7
| | | | | | | | Add a return value to pci_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-052-10/+10
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
generated by cgit (git 2.34.1) at 2026-01-05 21:52:50 +0000