summaryrefslogtreecommitdiffstats
path: root/drivers/net
Commit message (Collapse)AuthorAgeFilesLines
* net: luton: remove address translation after ofnode_read_resourcePatrick Delaunay2021-06-051-4/+1
| | | | | | | | | | | | Removed call of ofnode_translate_address() after ofnode_read_resource in luton_switch.c:luton_probe(); it is unnecessary since the commit feb7ac457c20 ("dm: core: Add address translation in fdt_get_resource"). Fixes: feb7ac457c20 ("dm: core: Add address translation in fdt_get_resource") Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reported-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
* net: Remove ne2000 driverTom Rini2021-05-256-1576/+0
| | | | | | | With the last user of this driver removed, remove the driver. Reviewed-by: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* net: mvpp2: add explicit sgmii-2500 supportMarcin Wojtas2021-05-201-16/+12
| | | | | | | | | | | | | | | | Until now the mvpp2 driver used an extra 'phy-speed' DT property in order to differentiate between the SGMII and SGMII @2.5GHz. As there is a dedicated PHY_INTERFACE_MODE_SGMII_2500 flag to mark the latter start using it and drop the custom flag. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Nadav Haklai <nadavh@marvell.com> Tested-by: Nadav Haklai <nadavh@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: mvpp2: allow MDIO registration for fixed linksStefan Chulski2021-05-201-4/+13
| | | | | | | | | | | | | | | | | | | | | | Currently, there are 2 valid cases for interface, PHY and mdio relation: - If an interface has PHY handler, it'll call mdio_mii_bus_get_from_phy(), which will register MDIO bus. - If we want to use fixed-link for an interface, PHY handle is not defined in the DTS, and no MDIO is registered. There is a third case, for some boards (with switch), the MDIO is used for switch configuration, but the interface itself uses fixed link. This patch allows this option by checking if fixed-link subnode is defined, in this case, MDIO bus is registers, but the PHY address is set to PHY_MAX_ADDR for this interface, so this interface will not try to access the PHY later on. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* net: mvpp2: fix missing switch case breakBen Peled2021-05-201-0/+2
| | | | | | | | Signed-off-by: Ben Peled <bpeled@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: mvpp2: remove unused define MVPP22_SMI_PHY_ADDR_REGBen Peled2021-05-201-3/+0
| | | | | | | | Signed-off-by: Ben Peled <bpeled@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: mvpp2: AN Bypass in 1000 and 2500 basex modeBen Peled2021-05-201-2/+4
| | | | | | | Signed-off-by: Ben Peled <bpeled@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* net: mvpp2: Fix 2.5G GMII_SPEED configurationsStefan Chulski2021-05-201-1/+2
| | | | | | | | | GMII_SPEED should be enabled for 2.5G speed Signed-off-by: Stefan Chulski <stefanc@marvell.com> Reviewed-by: Yan Markman <ymarkman@marvell.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* net: mvpp2: remove redundant SMI address configurationMarcin Wojtas2021-05-201-12/+0
| | | | | | | | | | | | Because the mvpp2 driver now relies on the PHYLIB and the external MDIO driver, configuring low level SMI bus settings is redundant. Signed-off-by: Marcin Wojtas <mw@semihalf.com> Reviewed-by: Kostya Porotchkin <kostap@marvell.com> Reviewed-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: mvpp2: add 1000BaseX and 2500BaseX ppv2 supportStefan Chulski2021-05-201-5/+112
| | | | | | Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: mvpp2: add CP115 port1 10G/5G SFI supportStefan Chulski2021-05-201-58/+17
| | | | | | | | | | | 1. Differ between Port1 RGMII and SFI modes in Netcomplex config. 2. Remove XPCS config from SFI mode. Port1 doesn't XPCS domain, XPCS config should be removed. Access to Port1 XPCS can cause stall. 3. Add Port1 MPCS configurations. Signed-off-by: Stefan Chulski <stefanc@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de>
* net: designware: meson8b: add g12a compatibleNeil Armstrong2021-05-141-0/+1
| | | | | | Add support for the Meson G12A dwmac glue compatible needed after Linux 5.12 sync. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* net: dwmac_meson8b: do not set TX delay in TXID & RXIDNeil Armstrong2021-05-141-4/+19
| | | | | | | | | When the PHY interface is set as TXID & RXID, the delays should be taken from DT, but first they should not be hardcoded since the PHY driver will set them. Fixes: 798424e857 ("net: designware: add Amlogic Meson8b & later glue driver") Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* Merge tag 'ti-v2021.07-rc3' of ↵Tom Rini2021-05-121-2/+3
|\ | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-ti - Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
| * net: ti: am65-cpsw-nuss: Add a new compatible for AM64Vignesh Raghavendra2021-05-121-0/+1
| | | | | | | | | | | | Add a new compatible to support AM64 SoC Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * net: ti: am65-cpsw-nuss: Don't cache disabled port IDVignesh Raghavendra2021-05-121-1/+1
| | | | | | | | | | | | | | | | Currently driver may end up caching disabled port ID as active interface. Fix this by bailing out earlier in case port is marked disabled in the DT. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
| * net: ti: am65-cpsw-nuss: Prepare to support non primary ext portVignesh Raghavendra2021-05-121-1/+1
| | | | | | | | | | | | | | | | | | CPSW NUSS IP on K3 SoCs can have more than one external port (upto 8) Therefore increase AM65_CPSW_CPSWNU_MAX_PORTS to 9 (8 ext + 1 Root port) as preparation to allow any one of the 8 ports to be used as ethernet interface in U-Boot. Signed-off-by: Vignesh Raghavendra <vigneshr@ti.com>
* | net: fec: Only unregister MII bus if we registered itSean Anderson2021-05-021-2/+6
| | | | | | | | | | | | | | | | | | | | | | If we fail to probe for whatever reason, we cannot unregister/free the MII bus unless we registered it with fec_get_miibus. This fixes FECs sharing an MDIO bus from destroying it, preventing the other FEC from using it. Fixes: 6a895d039b ("net: Update eQos driver and FEC driver to use eth phy interfaces") Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: fec: Don't use disabled physSean Anderson2021-05-021-6/+9
|/ | | | | | | If a phy is disabled, don't use it. This matches Linux's behavior. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* Merge tag 'dm-pull-29apr21' of ↵Tom Rini2021-04-294-12/+4
|\ | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-dm buildman environment fix binman FMAP improvements minor test improvements and fixes minor dm improvements
| * dm: core: Add address translation in fdt_get_resourcePatrick Delaunay2021-04-294-12/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Today of_address_to_resource() is called only in ofnode_read_resource() for livetree support and fdt_get_resource() is called when livetree is not supported. The fdt_get_resource() doesn't do the address translation so when it is required, but the address translation is done by ofnode_read_resource() caller, for example in drivers/firmware/scmi/smt.c::scmi_dt_get_smt_buffer() { ... ret = ofnode_read_resource(args.node, 0, &resource); if (ret) return ret; faddr = cpu_to_fdt32(resource.start); paddr = ofnode_translate_address(args.node, &faddr); ... The both behavior should be aligned and the address translation must be called in fdt_get_resource() and removed for each caller. Fixes: a44810123f9e ("dm: core: Add dev_read_resource() to read device resources") Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Acked-by: Etienne Carriere <etienne.carriere@linaro.org>
* | Merge tag 'xilinx-for-v2021.07-rc2' of ↵Tom Rini2021-04-291-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.07-rc2 xilinx: - Enable saving variables based on bootmode - Cleanup usb dfu setup and wire it up with usb bootmode - Fix bootscript address logic - Remove GD references (spi, Versal) - Enable capsule update clk: - Small Kconfig fix net: - Fix gmii2rgmii bridge binding usb: - Propagate error (dfu gadget)
| * | net: phy: xilinx: Break while loop over ethernet phyMichal Simek2021-04-291-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 6c993815bbea ("net: phy: xilinx: Be compatible with live OF tree") change driver behavior to while loop which wasn't correct because the driver was looping over again and again. The reason was that ofnode_valid() is taking 0 as correct value. Fix it by changing while loop to ofnode_for_each_subnode() which is only loop over available nodes. Fixes: 6c993815bbea ("net: phy: xilinx: Be compatible with live OF tree") Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | | net: designware: fix PHY reset with DM_MDIONeil Armstrong2021-04-281-4/+11
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | The dw_eth_pdata is not accessible from the mdio device, it gets the mdio bus plat leading to random sleeps (-10174464 on Odroid-HC4). This moves the dw_mdio_reset function to a common one taking the ethernet device as parameter and use it from the dw_mdio_reset and dm_mdio variant functions. Fixes: 5160b4567c ("net: designware: add DM_MDIO support") Reported-by: Mark Kettenis <mark.kettenis@xs4all.nl> Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: sun8i-emac: Fix pinmux setup for Allwinner H5Andre Przywara2021-04-261-2/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Commit eb5a2b671075 ("net: sun8i-emac: Determine pinmux based on SoC, not EMAC type") switched the pinmux setup over to look at CONFIG_MACH_SUN* symbols, to find the appropriate mux value. Unfortunately this patch missed to check for the H5, which is pin-compatible to the H3, but uses a different Kconfig symbol (because it has ARMv8 vs. ARMv7 cores). Replace the pure SUN8I_H3 symbol with the joint SUNXI_H3_H5 one, which is there to cover the peripherals common to both SoCs. Also explicitly list each supported SoC, and have an error message in the fallback case, to avoid those problems in the future. This fixes Ethernet support on all H5 boards. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Samuel Holland <samuel@sholland.org> # Orange Pi PC2 Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: jr2: Fix Serdes6G configurationHoratiu Vultur2021-04-221-4/+23
| | | | | | | | | | | | | | | | | | | | Sometimes no traffic was getting out on the ports, the root cause was a wrong configuration of the Serdes6G, which is used on jr2 pcb111. This patch fixes this issue by applying the correct configuration. Fixes: 5e1d417bec92ac ("net: Add MSCC Jaguar2 network driver.") Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* | net: jr2: Reset switchHoratiu Vultur2021-04-221-1/+15
|/ | | | | | | Make sure to reset the switch core at probe time. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: calxedagmac: Convert to DM_ETHAndre Przywara2021-04-202-64/+135
| | | | | | | | | | | | | | | | | | To squash that nasty warning message and make better use of the newly gained OF_CONTROL feature, let's convert the calxedagmac driver to the "new" driver model. The conversion is pretty straight forward, mostly just adjusting the use of the involved data structures. The only actual change is the required split of the receive routine into a receive and free_pkt part. Also this allows us to get rid of the hardcoded platform information and explicit init calls. This also uses the opportunity to wrap the code decoding the MMIO register base address, to make it safe for using PHYS_64BIT later. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: octeontx: smi: fix mii probeTim Harvey2021-04-201-0/+2
| | | | | | | | | The fdt node offset is apparently not set properly when probed causing no MDIO busses to be found. Fix this by obtaining the offset. Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Stefan Roese <sr@denx.de>
* drivers: net: octeontx: fix QSGMIITim Harvey2021-04-201-13/+7
| | | | | | | Revert a change that occured between the Marvell SDK-10.1.1.0 and SDK-10.3.1.1 which broke QSMII phy support. Signed-off-by: Tim Harvey <tharvey@gateworks.com>
* net: tsec: Support <reg> property from the subnode "queue-group"Bin Meng2021-04-151-3/+27
| | | | | | | | | | | | | | | | At present the tsec driver uses a non-standard DT bindings to get its <reg> base / size. The upstream Linux kernel seems to require the <reg> base / size to be put under a subnode of the eTSEC node with a name prefix "queue-group". This is not documented in the kernel DT bindings, but it looks every dtsi file that contains the eTSEC node was written like this. This commit updates the tsec driver to handle this case. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: tsec: Use map_physmem() directly instead of dev_remap_addr()Bin Meng2021-04-151-1/+3
| | | | | | | | | | | dev_remap_addr() eventually calls dev_read_addr_index(), while pdata->iobase holds the return value of dev_read_addr() that calls dev_read_addr_index() too. Such duplication can be avoided by using map_physmem() directly. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* sandbox: Add a DSA sandbox driver and unit testClaudiu Manoil2021-04-153-0/+189
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DSA sandbox driver is used for unit testing the DSA class code. It implements a simple 2 port switch plus 1 CPU port, and uses a very simple tag to identify the ports. The DSA sandbox device is connected via CPU port to a regular Ethernet sandbox device, called 'dsa-test-eth, managed by the existing eth sandbox driver. The 'dsa-test-eth' is not intended for testing the eth class code however, but it is used to emulate traffic through the 'lan0' and 'lan1' front pannel switch ports. To achieve this the dsa sandbox driver registers a tx handler for the 'dsa-test-eth' device. The switch ports, labeled as 'lan0' and 'lan1', are also registered as eth devices by the dsa class code this time. So pinging through these switch ports is as easy as: => setenv ethact lan0 => ping 1.2.3.5 Unit tests for the dsa class code were also added. The 'dsa_probe' test exercises most API functions from dsa.h. The 'dsa' unit test simply exercises ARP/ICMP traffic through the two switch ports, including tag injection and extraction, with the help of the dsa sandbox driver. I took care to minimize the impact on the existing eth unit tests, though some adjustments needed to be made with the addition of extra eth interfaces used by the dsa unit tests. The additional eth interfaces also require MAC addresses, these have been added to the sandbox default environment. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Message-Id: <20210216224804.3355044-5-olteanv@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: tsec: Use dm_eth_phy_connect() directly for the DM caseVladimir Oltean2021-04-151-5/+1
| | | | | | | | | | | | | | | Now that the fixed phy driver has been fully adapted to OF APIs, and dm_eth_phy_connect() already can handle the fixed phy, call dm_eth_phy_connect() directly in the DM tsec driver. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210216224804.3355044-4-olteanv@gmail.com> [bmeng: split from "net: mdio: teach dm_eth_phy_connect to connect to fixed PHY"] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: phy: fixed: Support the old DT bindingBin Meng2021-04-151-3/+23
| | | | | | | | | Update fixedphy_probe() to support the old DT binding. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: phy: fixed: Add the missing ending newlineBin Meng2021-04-151-1/+1
| | | | | | | | | The printf statement doesn't end with a newline. Add it. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: phy: fixed: Make driver ops staticBin Meng2021-04-151-4/+4
| | | | | | | | | The PHY driver ops should be made static. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: phy: Simplify the logic of phy_connect_fixed()Bin Meng2021-04-151-8/+8
| | | | | | | | | | | Simplify the logic of phy_connect_fixed() by using the new API ofnode_phy_is_fixed_link(), which brings additional bonus of supporting the old DT bindings. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: phy: xilinx: Drop #ifdef CONFIG_DM_ETH around phy_connect_gmii2rgmii()Bin Meng2021-04-152-6/+1
| | | | | | | | | | | | | At present phy_connect_gmii2rgmii() is implemented using a DM API dev_of_offset() hence it cannot support a non-DM configuration. Remove the non-DM version prototype of phy_connect_gmii2rgmii() and make the driver depend on CONFIG_DM_ETH. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: phy: xilinx: Be compatible with live OF treeBin Meng2021-04-152-44/+40
| | | | | | | | | Following the same updates that were done to the fixed phy driver, use ofnode_ APIs instead of fdt_ APIs so that the Xilinx PHY driver can support live DT. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: phy: fixed: Drop #ifdef CONFIG_DM_ETH around phy_connect_fixedVladimir Oltean2021-04-151-6/+0
| | | | | | | | | | | | | | | | In drivers/net/phy/Kconfig, CONFIG_PHY_FIXED already depends on CONFIG_DM_ETH, so the function prototype definition when CONFIG_DM_ETH=n does nothing, so it can be dropped. It is also never reachable, since the whole function is already under #ifdef CONFIG_PHY_FIXED (which again, as I said, depends on CONFIG_DM_ETH=y). Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210216224804.3355044-3-olteanv@gmail.com> Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* net: phy: fixed: Be compatible with live OF treeVladimir Oltean2021-04-152-24/+32
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On systems that use CONFIG_OF_LIVE, the "ofnode" type is defined as const struct device_node *np, while on the flat DT systems it is defined as a long of_offset into gd->fdt_blob. It is desirable that the fixed PHY driver uses the higher-level ofnode abstraction instead of parsing gd->fdt_blob directly, because that enables it to work on live OF systems. The fixed PHY driver has used a nasty hack since its introduction in commit db40c1aa1c10 ("drivers/net/phy: add fixed-phy / fixed-link support"), which is to pass the long gd->fdt_blob offset inside int phydev->addr (a value that normally holds the MDIO bus address at which the PHY responds). Even ignoring the fact that the types were already mismatched leading to a potential truncation (flat OF offset was supposed to be a long and not an int), we really cannot extend this hack any longer, because there's no way an int will hold the other representation of ofnode, the struct device_node *np. So we unfortunately need to do the right thing, which is to use the framework introduced by Grygorii Strashko in commit eef0b8a930d1 ("net: phy: add ofnode node to struct phy_device"). This will populate phydev->node for the fixed PHY. Note that phydev->node will not be valid in the probe function, since that is called synchronously from phy_device_create and we really have no way of passing the ofnode directly through the phy_device_create API. So we do what other drivers do too: we move the OF parsing logic from the .probe to the .config method of the PHY driver. The new function will be called at phy_config() time. I do believe I've converted all the possible call paths for creating a PHY with PHY_FIXED_ID, so there is really no reason to maintain compatibility with the old logic of retrieving a flat OF tree offset from phydev->addr. We just pass 0 to phydev->addr now. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Message-Id: <20210216224804.3355044-2-olteanv@gmail.com> [bmeng: keep fixedphy_probe(); update mdio-uclass.c to handle fixed phy] Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* ppc: Remove Cyrus_P5020 and P5040 boardsTom Rini2021-04-102-2/+0
| | | | | | | | | | | These boards have not been converted to CONFIG_DM_MMC by the deadline. Remove them. As the P5020 is the last ARCH_P5020 platform, remove that support as well. Cc: Andy Fleming <afleming@gmail.com> Cc: Priyanka Jain <priyanka.jain@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* ppc: Remove T2081QDS board and ARCH_T2081 supportTom Rini2021-04-102-2/+0
| | | | | | | | | | This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. It is also the only ARCH_T2081 board so remove that support as well. Cc: Shengzhou Liu <Shengzhou.Liu@nxp.com> Cc: Ruchika Gupta <ruchika.gupta@nxp.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* net: designware: remove amlogic compatiblesNeil Armstrong2021-04-061-3/+0
| | | | | | These compatibles are now handled by the dwmac_meson8b glue driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* net: designware: add Amlogic Meson8b & later glue driverNeil Armstrong2021-04-063-0/+159
| | | | | | | | | | | | | This adds a proper glue driver for the Designware DWMAC ethernet MAC IP found in the Amlogic Meson8, GXBB, GXL, GXM, G12A, G12B & SM1 SoCs. This is aimed to replace the static ethernet link setup found on the board init code for the Amlogic SoC based boards. Tested on a libretech-cc (S905x Internal RMII 10/100 PHY) and Khadas VIM3 (A113d with external 10/100/1000 RGMII PHY) to cover the most extreme setups. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* net: add Amlogic Meson G12A MDIO MUX driverNeil Armstrong2021-04-063-0/+157
| | | | | | | | | | The Amlogic G12A & compatible SoCs embeds a mux to either communicate with the external PHY or the internal 10/100 PHY. This adds support for this mux as a MDIO MUX device. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: designware: add DM_MDIO supportNeil Armstrong2021-04-061-1/+92
| | | | | | | | | Add support for DM_MDIO to connect to PHY and expose a MDIO device for the internal MDIO bus in order to dynamically connect to MDIO PHYs with DT with eventual MDIO muxes in between. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: add MMIO Register MDIO MUX driverNeil Armstrong2021-04-063-0/+137
| | | | | | | Add support for MMIO register MDIO muxes based on the Linux mdio-mux-mmioreg driver. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
* net: gem: Fix setting PCS auto-negotiation stateRobert Hancock2021-03-301-8/+17
| | | | | | | | | | | | | | | | | | | The code was trying to disable PCS auto-negotiation when a fixed-link node is present and enable it otherwise. However, the PCS registers were being written before the PCSSEL bit was set in the network configuration register, and it appears that in this state, PCS register writes are ignored. The result is that the intended change only took effect on the second network operation that was performed, since at that time PCSSEL is already enabled. Fix the order of register writes so that PCS registers are only written to after the PCS is enabled. Fixes: 26e62cc971 ("net: gem: Disable PCS autonegotiation in case of fixed-link") Signed-off-by: Robert Hancock <robert.hancock@calian.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Reviewed-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
generated by cgit (git 2.34.1) at 2025-06-13 16:20:55 +0000