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* net: Update to use new sequence numbersSimon Glass2020-12-181-1/+1
| | | | | | | | | | | Checking for seq == -1 is effectively checking that the device is activated. The new sequence numbers are never -1 for a bound device, so update the check. Also drop the note about valid sequence numbers so it is accurate with the new approach. Signed-off-by: Simon Glass <sjg@chromium.org>
* octeon: Don't attempt to set the sequence numberSimon Glass2020-12-181-1/+0
| | | | | | | | Several Octeon drivers operate by setting the sequence number of their device. This should not be needed with the new sequence number setup. Also it is not permitted. Drop it. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Avoid accessing seq directlySimon Glass2020-12-1813-20/+22
| | | | | | | | | | At present various drivers etc. access the device's 'seq' member directly. This makes it harder to change the meaning of that member. Change access to go through a function instead. The drivers/i2c/lpc32xx_i2c.c file is left unchanged for now. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-134-21/+21
| | | | | | | Try to maintain some consistency between these variables by using _plat as a suffix for them. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-1335-80/+80
| | | | | | | This name is far too long. Rename it to remove the 'data' bits. This makes it consistent with the platdata->plat rename. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2020-12-1361-166/+166
| | | | | | Rename this to be consistent with the change from 'platdata'. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-1362-67/+67
| | | | | | | | | | We use 'priv' for private data but often use 'platdata' for platform data. We can't really use 'pdata' since that is ambiguous (it could mean private or platform data). Rename some of the latter variables to end with 'plat' for consistency. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-1376-140/+140
| | | | | | | | | | | | This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: Remove uses of device_bind_offset()Simon Glass2020-12-131-2/+2
| | | | | | | This function is not needed since the standard device_bind() can be used instead. Signed-off-by: Simon Glass <sjg@chromium.org>
* dm: core: Rename device_bind() to device_bind_offset()Simon Glass2020-12-131-1/+1
| | | | | | | | | This function is not necessary anymore, since device_bind_ofnode() does the same thing and works with both flattree and livetree. Rename it to indicate that it is special. Signed-off-by: Simon Glass <sjg@chromium.org>
* net: ks8851: Implement EEPROM MAC address readoutMarek Vasut2020-11-091-0/+29
| | | | | | | | | | | In case there is an EEPROM attached to the KS8851 MAC and the EEPROM contains a valid MAC address, the MAC address is loaded into the NIC registers on power on. Read the MAC address out of the NIC registers and provide it to U-Boot. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2020-10-291-2/+2
|\ | | | | | | | | | | - Bug fixes and updates on vid, ls1088a lx2160a and other layerscape platforms. - Add optee_rpmb support for LX2 & Kontron sl28 support
| * net: lx2160a.c: Update to set ECx_PMUX precedenceRazvan Ionut Cirjan2020-10-231-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | As per hardware documentation, ECx_PMUX has precedence over SerDes protocol. For LX2160/LX2162 if DPMACs 17 and 18 are enabled as SGMII through SerDes protocol but ECx_PMUX configured them as RGMII, then the ports will be configured as RGMII and not SGMII. Signed-off-by: Razvan Ionut Cirjan <razvanionut.cirjan@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | Merge branch 'master' of https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2020-10-221-251/+206
|\ \ | |/ |/| | | | | - sun8i emac changes (Andre) - SCP firmware (Samuel)
| * net: sun8i-emac: Lower MDIO frequencyAndre Przywara2020-10-211-0/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When sending a command via the MDIO bus, the Designware MAC expects some bits in the CMD register to describe the clock divider value between the main clock and the MDIO clock. So far we were omitting these bits, resulting in setting "00", which means "/ 16", so ending up with an MDIO frequency of either 18.75 or 12.5 MHz. All the internal PHYs in the H3/H5/H6 SoCs as well as the Gbit Realtek PHYs seem to be fine with that - although it looks like to be severly overclocked (the MDIO spec limits the frequency to 2.5 MHz). However the external 100Mbit PHY on the Pine64 (non-plus) board is not happy with that, Ethernet was actually never working there, as the PHY didn't probe. As we set the EMAC clock (via AHB2) to 300 MHz in ATF (on the 64-bit SoCs), and use 200 MHz on the H3, we need the highest divider of 128 to let the MDIO clock end up below the required 2.5 MHz. This enables Ethernet on the Pine64(non-plus). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i-emac: Make internal PHY handling more robustAndre Przywara2020-10-211-32/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation of sun8i_get_ephy_nodes() makes quite some assumptions, in general relying on DT path names is a bad idea. I think the idea of the code was to determine if we are using the internal PHY, for which there are simpler and more robust methods: Rewrite (and rename) the existing function to simply lookup the DT node that "phy-handle" points to, using the device's DT node. Then check whether the parent of that PHY node is using an "H3 internal MDIO" compatible string. If we ever get another internal MDIO bus implementation, we will probably need code adjustments anyway, so this is good enough for now. Signed-off-by: Andre Przywara <andre.przywara@arm.com> [jagan: rebase on master] Signed-off-by: Jagan Teki <jagan@amarulasolutions.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Simplify and fix error handling for RXAndre Przywara2020-10-211-26/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The error handling in recv() is somewhat broken, for instance good_packet isn't really used, and it's hardly readable. Also we try to check for short or too big packets, but those are actually filtered out by the hardware. Simplify the whole routine and improve the error handling: - Bail out early if the current RX descriptor is not ready. - Enable propagation of runt, huge and broken packets. - Check for runt and huge packets, and return 0 to indicate this. This will force the framework to call free_pkt for cleanup. - Avoid aligning the packet buffer for invalidation again. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Fix MAC soft resetAndre Przywara2020-10-211-14/+7
| | | | | | | | | | | | | | | | | | | | | | | | The EMAC soft reset routine was subtly broken, using an open coded timeout routine without any actual delay. Remove the unneeded initial reset bit read, and call wait_for_bit_le32() to handle the timeout correctly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Fix overlong linesAndre Przywara2020-10-211-12/+10
| | | | | | | | | | | | | | | | | | | | | | | | When iterating over all RX/TX buffers, we were using a rather long "idx" control variable, which lead to a nasty overlong line. Replace "idx" with "i" to avoid this. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Wrap and simplify cache maintenance operationsAndre Przywara2020-10-211-19/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | To meet the current alignment requirements for our cache maintenance functions, we were explicitly aligning the *arguments* to those calls. This is not only ugly to read, but also wrong, as we need to make sure we are not accidentally stepping on other data. Provide wrapper functions for the common case of cleaning or invalidating a descriptor, to make the cache maintenance calls more readable. This fixes a good deal of the problematic calls. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Drop unneeded cache invalidation before sendingAndre Przywara2020-10-211-3/+0
| | | | | | | | | | | | | | | | | | | | | | | | There is no reason to invalidate a TX descriptor before we are setting it up, as we will only write to a field. Remove the not needed invalidate_dcache_range() call. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Reduce cache maintenance on TX descriptor initAndre Przywara2020-10-211-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When we initialise the TX descriptors, there is no need yet to clean them all to memory, as they don't contain any data yet. Later we will touch and clean each descriptor anyway. However we tell the MAC about the beginning of the chain, so we have to clean at least the first descriptor, to make it clear that this is empty and there are no packets to transfer yet. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Improve cache maintenance on RX descriptor initAndre Przywara2020-10-211-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | Before we initialise the RX descriptors, there is no need to *clean* them from the cache, as we touch them for the first time. However we should cover the case that those buffers contain dirty cache lines, which could be evicted and written back to DRAM any time later, in the worst case *after* the MAC has transferred a packet into them. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Name magic bits and simplify read-modify-write callsAndre Przywara2020-10-211-52/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The EMAC driver contains a lot of magic bits, although the manuals and the Linux driver have all names for them. Define those names and use them when programming the registers. Also this replaces a lot of readl/mask/writel operations with the much easier-to-read setbits_le32() macro. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Remove pointless wrapper functionsAndre Przywara2020-10-211-46/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Apparently due to copying from some older or converted driver, the sun8i_emac driver contains pointless wrapper functions to bridge between a legacy driver and the driver model. Since sun8i_emac is (and always was) driver model only, there is no reason to have those confusing wrappers. Just remove them, and use the driver model prototypes directly. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Simplify mdio_read/mdio_write functionsAndre Przywara2020-10-211-41/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When preparing the register value for the MDIO command register, we start with a zeroed register, so there is no need to mask off certain bits before setting them. Simplify the sequence, and rename the variable to a more matching mii_cmd on the way. Also the open-coded time-out routine can be replaced with a much safer and easier-to-read call to wait_for_bit_le32(). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i_emac: Don't hand out TX descriptor too earlyAndre Przywara2020-10-211-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When initialising the TX DMA descriptors, we mostly chain them up, but of course don't know about any data or its length yet. That means they are still invalid, and the OWN bit should NOT be set yet. In fact when we later tell the MAC about the beginning of the chain, and enable TX DMA in the start() routine, the MAC will start fetching TX descriptors prematurely, as it can be seen by dumping the TX_DMA_STA and TX_DMA_CUR_DESC registers. Clear the owner bit, to not give the MAC the wrong illusion that it owns the descriptors already. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
| * net: sun8i-emac: Bail out on PHY errorAndre Przywara2020-10-211-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | When phy_startup() returns with an error, because there is no link or the user interrupted the process, we shall stop the _start() routine and return with an error, instead of proceeding anyway. This fixes pointless operations when there is no Ethernet cable connected, for instance. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Maxime Ripard <mripard@kernel.org> Tested-by: Amit Singh Tomar <amittomer25@gmail.com> # Pine64+ Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | net: Add IPQ40xx MDIO driverRobert Marko2020-10-223-0/+154
|/ | | | | | | | This adds the driver for the IPQ40xx built-in MDIO. This will be needed to support future PHY driver. Signed-off-by: Robert Marko <robert.marko@sartura.hr> Cc: Luka Perkov <luka.perkov@sartura.hr>
* net: ldpaa_eth: Include device_compat.hSean Anderson2020-10-151-7/+7
| | | | | | Necessary for dev_xxx. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-marvellTom Rini2020-10-1428-0/+11149
|\ | | | | | | | | | | | | | | | | | | | | - Octeon TX: Add NAND driver (Suneel) - Octeon TX: Add NIC driver driver (Suneel) - Octeon TX2: Add NIC driver driver (Suneel) - Armada 8040: Add iEi Puzzle-M80 board support (Luka) - Armada A37xx SPI: Add support for CS-GPIO (George) - Espressobin: Use Linux model/compatible strings (Andre) - Espressobin: Add armada-3720-espressobin-emmc.dts from Linux (Andre) - Armada A37xx: Small cleanup of config header (Pali)
| * net: Add NIC controller driver for OcteonTX2Suneel Garapati2020-10-1416-0/+4493
| | | | | | | | | | | | | | | | | | Adds support for Network Interface controllers found on OcteonTX2 SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
| * net: Add NIC controller driver for OcteonTXSuneel Garapati2020-10-1414-0/+6656
| | | | | | | | | | | | | | | | | | Adds support for Network Interface controllers found on OcteonTX SoC platforms. Signed-off-by: Suneel Garapati <sgarapati@marvell.com> Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com>
* | net: e1000: add defaults for i210 TX/RX PBSIZEChristian Gmeiner2020-10-142-0/+11
|/ | | | | | | | | | | | | | | | | Set the defaults on probe for the packet buffer size registers for the i210. The TX/RX PBSIZE register of the i210 resets to its default value only at power-on - see Intel Ethernet Controller I210 Datasheet rev 3.5 chapter 8.3 'Internal Packet Buffer Size Registers'. If something (another driver, another OS, etc.) modifies this register from its default value, the e1000 driver doesn't function correctly. It detects a hang of the transmitter and continuously resets the adapter. Here we set this value to its default when resetting the i210 to resolve this issue. Signed-off-by: Christian Gmeiner <christian.gmeiner@gmail.com>
* dm: add cells_count parameter in *_count_phandle_with_argsPatrick Delaunay2020-10-061-1/+2
| | | | | | | | | | | | | | | | | | | The cell_count argument is required when cells_name is NULL. This patch adds this parameter in live tree API - of_count_phandle_with_args - ofnode_count_phandle_with_args - dev_count_phandle_with_args This parameter solves issue when these API is used to count the number of element of a cell without cell name. This parameter allow to force the size cell. For example: count = dev_count_phandle_with_args(dev, "array", NULL, 3); Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge branch 'next'Tom Rini2020-10-0525-167/+2976
|\ | | | | | | | | | | | | Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
| * Revert "net: smc911x: Automatically Update ethaddr with MAC"Tom Rini2020-10-011-3/+0
| | | | | | | | | | | | | | | | | | | | | | Upon further discussion on the mailing list, we should not get in the situation where the generic code path to set ethaddr/etc correctly does not work. Revert this until someone can further debug the smc911x driver regarding this issue. This reverts commit 387cbf096e443705fa66776027273ed257ec6ca3. Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge branch 'next' of git://git.denx.de/u-boot-sh into nextTom Rini2020-10-011-2/+0
| |\
| | * net: ravb: Remove writeext function callBiju Das2020-09-261-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | The micrel phy driver is already configuring this values from device tree. So remove the redundant phy configuration call from this driver. Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com> Reviewed-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
| * | net: dwc_eth_qos: Convert to use APIs which support live DTPatrick Delaunay2020-09-301-4/+3
| | | | | | | | | | | | | | | | | | | | | Use ofnode_ or dev_ APIs instead of fdt_ and fdtdec_ APIs so that the driver can support live DT. Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | net: smc911x: Automatically Update ethaddr with MACAdam Ford2020-09-301-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The ethernet controller can read the MAC from EEPROM and display it, but if ethaddr is not set, the ethernet is still unavailable. This patch checks will automatically set the MAC address if it has not already been set. Signed-off-by: Adam Ford <aford173@gmail.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
| * | net: ftgmac100: Add support for board specific PHY interface addressThirupathaiah Annapureddy2020-09-301-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ftgmac100 driver is using hard-coded PHY interface address of zero. Each board can have different PHY interface address (phy_addr). This commit modifies the driver to make use of board specific address by leveraging CONFIG_PHY_ADDR. Signed-off-by: Thirupathaiah Annapureddy <thiruan@linux.microsoft.com> Reviewed-by: Cédric Le Goater <clg@kaod.org>
| * | net: phy: mscc: sync rx/tx delay settings with Linux on vsc85xxHeiko Stuebner2020-09-301-24/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Linux kernel does set the clock delays to - 0.2 ns (their default, and lowest, hardware value) if delays should not be enabled - 2.0 ns (which causes the data to be sampled at exactly half way between clock transitions at 1000 Mbps) if delays should be enabled depending on the interface mode See https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/net/phy/mscc/mscc_main.c#n523 So instead of using arbitrary delay values like now, mimic this behaviour. The behaviour is the same for all of vsc8530/8531/8540/8541 so move that to a shared function while at it. Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | net: phy: mscc: make clock-output configurable on vsc85xxHeiko Stuebner2020-09-301-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The vsc8530/8531/8540/8541 phys have a configurable clock output that can emit 25, 50 and 125 MHz rates, which in turn may be needed for stable network connections. This follows a similar change introduced into the Linux kernel at https://lore.kernel.org/netdev/20200609133140.1421109-2-heiko@sntech.de Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
| * | net: ti: cpsw: Fix not calling dev_dbg with a deviceSean Anderson2020-09-301-0/+6
| | | | | | | | | | | | | | | | | | | | | Without DM_ETH, cpsw_priv.dev is an eth_device. Just use its name instead. Signed-off-by: Sean Anderson <seanga2@gmail.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | net: sun8i_emac: Fix not calling dev_xxx with a deviceSean Anderson2020-09-301-4/+5
| | | | | | | | | | | | | | | | | | | | | | | | Pass a udevice into a few functions so `dev` is defined. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | net: sunxi: Fix not calling dev_xxx with a deviceSean Anderson2020-09-301-2/+3
| | | | | | | | | | | | | | | | | | | | | | | | There's no dev to log with, so pass the device along with the priv data. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | net: mvpp2: Convert netdev_xxx to dev_xxxSean Anderson2020-09-301-31/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | netdev_xxx evaluates to printf in U-Boot, so there is no extra info printed. mvpp2 one of only two drivers which use these functions in U-Boot. Convert these functions to dev_xxx where possible (and to log_xxx where not). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | net: mvpp2: Fix not calling dev_xxx with a deviceSean Anderson2020-09-301-11/+12
| | | | | | | | | | | | | | | | | | | | | | | | Remove some prefixes, or get the device from the phy. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
| * | net: mvneta: Convert netdev_xxx to dev_xxxSean Anderson2020-09-301-24/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | netdev_xxx evaluates to printf in U-Boot, so there is no extra info printed. mvneta is one of two drivers which use these functions in U-Boot. Convert these functions to dev_xxx where possible (and to log_xxx where not). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Patrick Delaunay <patrick.delaunay@st.com>
generated by cgit (git 2.34.1) at 2024-09-22 03:27:46 +0000