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* net: cortina_ni: buffer overrunHeinrich Schuchardt2021-02-241-1/+1
| | | | | | | | | | | | When copying to a u32 field we should use sizeof(u32) and not sizeof(*u32) in memcpy. On 64bit systems like cortina_presidio-asic-emmc_defconfig using sizeof(*u32) leads to a buffer overrun. Fixes: febe13b438b3 ("net: cortina_ni: Add eth support for Cortina Access CAxxxx SoCs") Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-By: Ramon Fried <rfried.dev@gmail.com>
* Merge tag 'xilinx-for-v2021.04-rc3' of ↵Tom Rini2021-02-231-12/+35
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name
| * net: gem: Fix error path in zynq_gem_probeMichal Simek2021-02-231-4/+4
| | | | | | | | | | | | | | Clean up error path in connection where priv->rxbuffers and priv->tx_bd are allocated. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: gem: Enable ethernet rx clock for versalT Karthik Reddy2021-02-231-6/+27
| | | | | | | | | | | | | | | | | | Enable rx clock along with tx clock for versal platform. Use compatible data to enable/disable clocks in the driver. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Ramon Fried <rfried.dev@gmail.com>
| * clk: zynq: Add dummy clock enable functionMichal Simek2021-02-231-2/+2
| | | | | | | | | | | | | | | | | | A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
| * net: gem: unregister mdio bus if probe failsMichael Walle2021-02-111-1/+3
| | | | | | | | | | | | | | | | If probe fails, the mdio bus isn't unregistered. Fix it. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Ramon Fried <rfried.dev@gmail.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | uec.h: fix COFIG_DM typoRasmus Villemoes2021-02-211-1/+1
| | | | | | | | | | Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Heiko Schocher <hs@denx.de>
* | dm_qe_uec.c: fix indentation in uec_set_mac_if_mode()Rasmus Villemoes2021-02-211-2/+2
| | | | | | | | | | Signed-off-by: Rasmus Villemoes <rasmus.villemoes@prevas.dk> Reviewed-by: Heiko Schocher <hs@denx.de>
* | drivers: net: Add Felix DSA switch driverAlex Marginean2021-02-164-0/+428
| | | | | | | | | | | | | | | | | | | | | | | | This driver is used for the Ethernet switch integrated into LS1028A NXP. Felix on LS1028A has 4 front panel ports and two internal ports, I/O to/from the switch is done through an ENETC Ethernet interface. The 4 front panel ports are available as Ethernet interfaces and can be used with the typical network commands like tftp. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
* | net: Introduce DSA class for Ethernet switchesClaudiu Manoil2021-02-161-0/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DSA stands for Distributed Switch Architecture and it covers switches that are connected to the CPU through an Ethernet link and generally use frame tags to pass information about the source/destination ports to/from CPU. Front panel ports are presented as regular ethernet devices in U-Boot and they are expected to support the typical networking commands. DSA switches may be cascaded, DSA class code does not currently support this. Signed-off-by: Alex Marginean <alexandru.marginean@nxp.com> Signed-off-by: Claudiu Manoil <claudiu.manoil@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
* | net: phy: introduce fixed_phy_create for DSA CPU portsVladimir Oltean2021-02-161-0/+31
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DSA (Distributed Switch Architecture) implementation has made a design decision when it got introduced to the Linux kernel in 2008. That was to hide away from the user the CPU-facing Ethernet MAC, since it does not make sense to register it as a struct net_device (UCLASS_ETH udevice for U-Boot), because that would never be beneficial for a user: they would not be able to use it for traffic, since conceptually, a packet delivered to the CPU port should loop back into the system. Nonetheless, DSA has had numerous growing pains due to the lack of a struct net_device for the CPU port, but so far it has overcome them. It is unlikely at this stage of maturity that this aspect of it will change. We would like U-Boot to present the same information as Linux, to be at parity in terms of number of interfaces, so that ethNaddr environment variables could directly be associated between U-Boot and Linux. Therefore, we would implicitly like U-Boot to hide the CPU port from the user as well. But the paradox is that DSA still needs a struct phy_device to inform the driver of the parameters of the link that it should configure the CPU port to. The problem is that the phy_device is typically returned via a call to phy_connect, which needs an udevice to attach the PHY to, and to search its ofnode for the 'fixed-link' property. But we don't have an udevice to present for the CPU port. Since 99% of DSA setups are MAC-to-MAC connections between the switch and the host Ethernet controller, the struct phy_device is going to be a fixed PHY. This simplifies things quite a bit. In U-Boot, a fixed PHY does not need an MDIO bus, and does not need an attached dev either. Basically, the phy_connect call doesn't do any connection, it just creates the fixed PHY. The proposal of this patch is to introduce a new fixed_phy_create function which will take a single argument: the ofnode that holds this: port@4 { reg = <4>; phy-mode = "internal"; fixed-link { speed = <2500>; full-duplex; }; }; and probe a fixed PHY driver using the information from this ofnode. DSA will probably be the only user of this function. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
* | net: phy: fixed: support speeds of 2500 and 10000Vladimir Oltean2021-02-161-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | Unlike the Linux fixed PHY driver, the one in U-Boot does not attempt to emulate the clause 22 register set of a gigabit copper PHY driver through the swphy framework. Therefore, the limitation of being unable to support speeds higher than gigabit in fixed-link does not apply to the U-Boot fixed PHY driver. This makes the fixed-link U-Boot implementation more similar to the one from phylink, which can work with any valid link speed. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Claudiu Manoil <claudiu.manoil@nxp.com>
* | image: Adjust the workings of fit_check_format()Simon Glass2021-02-152-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present this function does not accept a size for the FIT. This means that it must be read from the FIT itself, introducing potential security risk. Update the function to include a size parameter, which can be invalid, in which case fit_check_format() calculates it. For now no callers pass the size, but this can be updated later. Also adjust the return value to an error code so that all the different types of problems can be distinguished by the user. Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Bruce Monroe <bruce.monroe@intel.com> Reported-by: Arie Haenel <arie.haenel@intel.com> Reported-by: Julien Lenoir <julien.lenoir@intel.com>
* | Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-1533-2/+34
|\ \ | | | | | | | | | - Merge the patch to take <asm/global_data.h> out of <common.h>
| * | common: Drop asm/global_data.h from common headerSimon Glass2021-02-0233-2/+34
| |/ | | | | | | | | | | | | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | sh: Remove sh7757lcr boardTom Rini2021-02-151-4/+0
| | | | | | | | | | | | | | | | | | | | This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it. As this is the last SH4A board, remove that support as well. Cc: Marek Vasut <marek.vasut+renesas@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* | sh: Remove r7780mp boardTom Rini2021-02-153-211/+0
| | | | | | | | | | | | | | | | | | This board has not been converted to CONFIG_DM by the deadline of v2020.01 and is missing other conversions which depend on this as well. Remove it. Patch-cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Patch-cc: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | net: eqos: Reduce the MDIO wait timeYe Li2021-02-081-1/+1
| | | | | | | | | | | | | | | | | | | | Current MDIO wait time is too long, which introduce long delay when PHY negotiation register checking. Reduce it to 10us Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Fugang Duan <Fugang.duan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | net: memac_phy: add a timeout to MDIO operationsIoana Ciornei2021-02-081-18/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We have encountered circumstances when a board design does not include pull-up resistors on the external MDIO buses which are not used. This leads to the MDIO data line not being pulled-up, thus the MDIO controller will always see the line as busy. Without a timeout in the MDIO bus driver, the execution is stuck in an infinite loop when any access is initiated on that external bus. Add a timeout in the driver so that we are protected in this circumstance. This is similar to what is being done in the Linux xgmac_mdio driver. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com> Reviewed-by: Madalin Bucur <madalin.bucur@oss.nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | net: ftmac100: Cast priv->iobase with uintptr_tBin Meng2021-02-031-5/+5
|/ | | | | | | | | | | | priv->iobase was declared as phys_addr_t which is now a 64-bit address. In a 32-bit build, this causes the following warning seen when building ftmac100.c: warning: cast to pointer from integer of different size [-Wint-to-pointer-cast] Cast priv->iobase with uintptr_t. Signed-off-by: Bin Meng <bin.meng@windriver.com>
* net: sun8i-emac: Determine pinmux based on SoC, not EMAC typeAndre Przywara2021-01-311-8/+20
| | | | | | | | | | | | | | The pinmux choice for the RMII/RGMII pins the EMAC is connected to is not dependent on the EMAC IP, but on the SoC it is integrated in. Deriving the pinmux from the DT compatible string (as we do at the moment) will thus cause problems with certain EMAC IP / SoC combinations. To avoid this exact issue with the H616, let's use our Kconfig MACH symbols to choose the correct pinmux setup. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
* net: sun8i-emac: Always clear syscon EPHY registerAndre Przywara2021-01-311-18/+13
| | | | | | | | | | | | | | | | | | At the moment we only consider the EPHY register for those SoCs were we actually have an internal PHY to configure. However even other SoCs have this register, an expect the EPHY select bit to be cleared for proper operation with an external PHY. Rework sun8i_emac_set_syscon_ephy() to be called regardless of the EMAC model, and clear the H3_EPHY_SELECT bit if no internal PHY is used. We get away without it so far because SoCs like the A64 clear this bit on reset, but we need to explicitly clear it on the H616, for instance. The Linux driver does so as well. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Tested-by: Jernej Skrabec <jernej.skrabec@siol.net> Reviewed-by: Jernej Skrabec <jernej.skrabec@siol.net>
* net: phy: micrel: Try default PHY ofnode firstMarek Vasut2021-01-271-2/+7
| | | | | | | | | | | The phydev structure has a PHY OF node pointer in it, use that OF node first when looking up PHY OF node properties, since that is likely the correct PHY OF node pointer. If the pointer is not valid, which is the case e.g. on legacy DTs, fall back to parsing MAC ethernet-phy subnode. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Ramon Fried <rfried.dev@gmail.com>
* net: phy: ca_phy: Add driver for CAxxxx SoCsAbbie Chang2021-01-274-0/+144
| | | | | | | | | | | | | | Add phy driver support for MACs embedded inside Cortina Access SoCs Signed-off-by: Abbie Chang <abbie.chang@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Tom Rini <trini@konsulko.com> CC: Aaron Tseng <aaron.tseng@cortina-access.com> Moved out PHY specific code out of Cortina NI Ethernet driver and into a Cortina Access PHY interface driver
* net: cortina_ni: Add eth support for Cortina Access CAxxxx SoCsAaron Tseng2021-01-274-0/+1512
| | | | | | | | | | | | | Add Cortina Access Ethernet device driver for CAxxxx SoCs. This driver supports both legacy and DM_ETH network models. Signed-off-by: Aaron Tseng <aaron.tseng@cortina-access.com> Signed-off-by: Alex Nemirovsky <alex.nemirovsky@cortina-access.com> Signed-off-by: Abbie Chang <abbie.chang@cortina-access.com> CC: Joe Hershberger <joe.hershberger@ni.com> CC: Abbie Chang <abbie.chang@Cortina-Access.com> CC: Tom Rini <trini@konsulko.com>
* net: e1000: Add missing address translationsStefan Roese2021-01-271-5/+5
| | | | | | | | | | | | | | Add some missing address translations from virtual address in local DRAM to physical address, which is needed for the DMA transactions to work correctly. This issue was detected while testing the e1000 driver on the MIPS Octeon III platform, which needs address translation. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
* net: e1000: Use virt_to_phys() instead of pci_virt_to_mem()Stefan Roese2021-01-271-7/+1
| | | | | | | | | | | | | | | | | Using (dm_)pci_virt_to_mem() is incorrect to translate the virtual address in local DRAM to a physical address. The correct macro here is virt_to_phys() so switch to using this macro. As virt_to_bus() is now not used any more, this patch also removes both definitions (DM and non-DM). This issue was detected while testing the e1000 driver on the MIPS Octeon III platform, which needs address translation. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
* net: e1000: Remove unused bus_to_phys() macroStefan Roese2021-01-271-2/+0
| | | | | | | | | | bus_to_phys() is defined but not referenced at all. This patch removes it completely. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
* Merge https://gitlab.denx.de/u-boot/custodians/u-boot-sunxiTom Rini2021-01-251-0/+3
|\ | | | | | | | | | | | | | | - New Allwinner H616 SoC support (sans Ethernet & USB) - H6 DT update - Tanix TX6 TV box support - OrangePi 3 support - OrangePi Zero2 (H616) support
| * net: sun8i-emac: Allow all RGMII PHY modesAndre Przywara2021-01-251-0/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far all GBit users of the sun8i-emac driver were using the "rgmii" PHY mode, even though this turns out to be wrong. It just worked because the PHY driver doesn't do the proper setup (yet). In fact for most boards the "rgmii-id" or "rgmii-txid" PHY modes are the correct ones. To allow the DTs to describe the phy-mode correctly, and to stay compatible with Linux, at least allow those other RGMII modes in the driver. This avoids breakage if mainline DTs will be synced with U-Boot. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Acked-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
* | Merge tag 'mips-pull-2021-01-24' of ↵Tom Rini2021-01-253-0/+1235
|\ \ | |/ |/| | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mips - MIPS: add support for Mediatek MT7620 SoCs
| * net: add ethernet driver for MediaTek MT7620 SoCWeijie Gao2021-01-243-0/+1235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds ethernet driver for MediaTek MT7620 SoC. The MT7620 SoC has a built-in ethernet (Frame Engine) and a built-in 7-port switch and two xMII interfaces (can be MII/RMII/RGMII). The port 0-3 of the switch connects to intergrited FE PHYs. Port 4 can be configured to connect to either the intergrited FE PHY, or the xMII. Port 5 always connects to the xMII. Port 6 is the CPU port. This driver supports MT7530 giga switch connects to port 5. Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Weijie Gao <weijie.gao@mediatek.com>
* | Merge tag 'u-boot-atmel-2021.04-b' of ↵Tom Rini2021-01-252-15/+150
|\ \ | |/ |/| | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel features for 2021.04 cycle This feature set includes macb updates for all interfaces and new sama7g5 variant support; micrel ksz9031 DLL support; a new board from Giant based on Adafruit feather form factor which contains a SAMA5D27 SoC; several fixes regarding the NAND flash PMECC block; and pincontrol drive strength support for pio4 controller.
| * net: macb: take into account all RGMII interface typesClaudiu Beznea2021-01-221-1/+4
| | | | | | | | | | | | | | Take into account all RGMII interface types. Depending on it the RGMII PHY's timings are setup. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * net: macb: add support for sama7g5 emacClaudiu Beznea2021-01-221-0/+9
| | | | | | | | | | | | Add support for SAMA7G5 EMAC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * net: macb: add support for sama7g5 gmacClaudiu Beznea2021-01-221-0/+33
| | | | | | | | | | | | Add support for SAMA7G5 GMAC. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * net: macb: check clk_set_rate return value to be negativeClaudiu Beznea2021-01-221-1/+1
| | | | | | | | | | | | | | | | | | clk_set_rate() returns the set rate in case of success and a negative number in case of failure. Consider failure only the negative numbers. Fixes: 3ef64444de157 ("dm: net: macb: Implement link speed change callback") Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * net: macb: add user io config data structureClaudiu Beznea2021-01-221-12/+41
| | | | | | | | | | | | | | | | | | | | Different implementation of USER IO register needs different mapping for bit fields of this register. Add implementation for this and, since clken is part of USER IO and it needs to be activated based on per SoC capabilities, add caps in macb_config where clken specific information needs to be filled. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * net: phy: micrel: fix typoClaudiu Beznea2021-01-191-1/+1
| | | | | | | | | | | | Fix typo. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
| * net: phy: micrel: add support for DLL setup on ksz9131Claudiu Beznea2021-01-191-1/+62
| | | | | | | | | | | | Add support for DLL setup on KSZ9131. Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
* | net: dwc_eth_qos: Pad descriptors to cacheline sizeMarek Vasut2021-01-191-78/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The DWMAC4 IP has the possibility to skip up to 7 AXI bus width size words after the descriptor. Use this to pad the descriptors to cacheline size and remove the need for noncached memory altogether. Moreover, this lets Tegra use the generic cache flush / invalidate operations. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Patrice Chotard <patrice.chotard@st.com> Cc: Patrick Delaunay <patrick.delaunay@st.com> Cc: Ramon Fried <rfried.dev@gmail.com> Cc: Stephen Warren <swarren@nvidia.com> Tested-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Stephen Warren <swarren@nvidia.com> Tested-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | net: ks8851: Reset internal RXFC count on bad packetMarek Vasut2021-01-191-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A sporadic condition occurs when the "bad packet" error is triggered repeatedly, which results in "bad packet" messages scrolling on the console during transfer. To avoid triggering this, reset the internal RXFC count on the first occurance of the "bad packet", which forces the code to re-read the RX packet count from the MAC, and prevents any additional "bad packet" messages if there are no more packets in the MAC. Also print better debug information if this condition occurs. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Eugen Hristev <eugen.hristev@microchip.com> Cc: Joe Hershberger <joe.hershberger@ni.com> Cc: Tom Rini <trini@konsulko.com>
* | net: ftgmac100: Read and retain MAC addressHongwei Zhang2021-01-191-0/+32
| | | | | | | | | | | | Read and retain MAC address across flash and QEMU support. Signed-off-by: Hongwei Zhang <hongweiz@ami.com>
* | net: e1000: implement eth_write_hwaddr for DM_ETHIan Ray2021-01-191-3/+14
|/ | | | | | | | | Implement programming MAC address to the hardware also for device model configuration. Fixes: b565b18a294f ("board: ge: bx50v3: Enable DM for PCI and ethernet") Signed-off-by: Ian Ray <ian.ray@ge.com> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com>
* net: macb: Add phy address to read it from device treePadmarao Begari2021-01-181-0/+13
| | | | | | | | | | Read phy address from device tree and use it to find the phy device if not found then search in the range of 0 to 31. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Reviewed-by: Bin Meng <bin.meng@windriver.com> Tested-by: Bin Meng <bin.meng@windriver.com>
* net: macb: Add DMA 64-bit address support for macbPadmarao Begari2021-01-182-17/+120
| | | | | | | | | | | | | | Enable 32-bit or 64-bit DMA in the macb driver based on the macb hardware compatibility and it is configured with structure macb_config in the driver. The Microchip PolarFire SoC Memory Protection Unit(MPU) gives the 64-bit DMA access with the GEM, the MPU transactions on the AXI bus is 64-bit not 32-bit So 64-bit DMA is enabled for the Microchip PolarFire SoC GEM. Signed-off-by: Padmarao Begari <padmarao.begari@microchip.com> Reviewed-by: Anup Patel <anup.patel@wdc.com> Tested-by: Bin Meng <bin.meng@windriver.com>
* common: board_r: Drop initr_bbmii wrapperOvidiu Panait2021-01-151-1/+3
| | | | | | | | Add a return value to bb_miiphy_init and use it directly in the post-relocation init sequence, rather than using a wrapper stub. Signed-off-by: Ovidiu Panait <ovidiu.panait@windriver.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* net: designware: socfpga: Add ATF support for MAC driverChee Hong Ang2021-01-151-6/+31
| | | | | | | | In non-secure mode (EL2), MAC driver calls the SMC/PSCI services provided by ATF to setup the PHY interface. Signed-off-by: Chee Hong Ang <chee.hong.ang@intel.com> Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* Merge tag 'dm-pull-5jan21' of git://git.denx.de/u-boot-dm into nextTom Rini2021-01-0515-45/+92
|\ | | | | | | | | | | | | | | | | Driver model: make some udevice fields private Driver model: Rename U_BOOT_DEVICE et al. dtoc: Tidy up and add more tests ns16550 code clean-up x86 and sandbox minor fixes for of-platdata dtoc prepration for adding build-time instantiation
| * dm: core: Access device ofnode through functionsSimon Glass2021-01-058-14/+15
| | | | | | | | | | | | | | | | At present ofnode is present in the device even if it is never used. With of-platdata this field is not used, so can be removed. In preparation for this, change the access to go through inline functions. Signed-off-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2024-11-17 15:16:13 +0000