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* Merge tag 'ti-v2021.07-rc3' of ↵Tom Rini2021-05-121-0/+18
|\ | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-ti - Initial support for AM64 EVM and SK - K3 DDR driver unification for J7 and AM64 platforms. - Minor fixes for TI clock driver
| * mmc: sdhci_am654: Add Support for TI's AM642 SoCDave Gerlach2021-05-121-0/+18
| | | | | | | | | | | | | | | | | | | | Add support for the controller present on the AM642 SoC. There are instances: sdhci0: 8bit bus width, max 400 MBps sdhci1: 4bit bus width, max 100 MBps Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
* | DM: DM_MMC migration is now mandatory for non-SPLTom Rini2021-05-111-0/+2
|/ | | | | | | | | As it has been now two years past the migration deadline, it is required to have migrated. Remove the check from the Makefile and rework some of the Kconfig logic slightly to get the functional dependencies of DM_MMC / BLK right in both the SPL and non-SPL case. Signed-off-by: Tom Rini <trini@konsulko.com>
* mmc: octeontx_hsmmc: Add support for MIPS OcteonStefan Roese2021-04-222-56/+149
| | | | | | | | | | | | | | | | | | | Until now, the Octeontx MMC driver did only support the ARM Octeon TX/Tx2 platforms. This patch adds support for the MIPS Octeon platform to this driver. Here a short summary of the changes: - Enable driver compilation for MIPS Octeon, including the MMC related header file - Reorder header inclusion - Switch to using the clk framework to get the input clock - Remove some functions for MIPS Octeon, as some registers don't exist here Signed-off-by: Stefan Roese <sr@denx.de> Cc: Peng Fan <peng.fan@nxp.com> Cc: Aaron Williams <awilliams@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com> Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com>
* arm: Remove s32v234evb boardTom Rini2021-04-101-1/+1
| | | | | | | | This board has not been converted to CONFIG_DM_MMC by the deadline. Remove it. Cc: Eddy Petrișor <eddy.petrisor@gmail.com> Signed-off-by: Tom Rini <trini@konsulko.com>
* Merge tag 'u-boot-imx-20210409' of ↵Tom Rini2021-04-091-17/+33
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx u-boot-imx-20210409 ------------------- - Secure Boot : - HAB for MX8M / MX7ULP - CAAM fixes - Fixes for imxrt1020 - Fixes for USDHC driver - Fixes for Toradex (Colibri / Apalis) - Switch to DM for several boards - mx23 olinuxo - usbarmory - marsboard / riotboard - Gateworks GW Ventana - NXP upstream patches (LPDDR / CAAM / HAB) CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/7089
| * mmc: fsl_esdhc_imx: add extra delay for IO voltage switch if necessaryHaibo Chen2021-04-081-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | Some board like imx8mm-evkb, IO voltage switch from 3.3v to 1.8v need around 18ms, common code only delay 10ms, so need to delay extra 8ms. Otherwise voltage switch will timeout when wait for data0 line. This IO voltage switch time depends on board design, depend on the PMIC and capacitance. imx8mm-evkb board use PCA9450(PMIC) and 10uF capacitance. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * mmc: fsl_esdhc_imx: remove redundant cmd11 related code.Haibo Chen2021-04-081-9/+0
| | | | | | | | | | | | | | Common code already handle the voltage switch sequence based on spec, so remove the redundant voltage switch code. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * mmc: fsl_esdhc_imx: use VENDORSPEC_FRC_SDCLK_ON to control card clock outputHaibo Chen2021-04-081-8/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For FSL_USDHC, it do not implement VENDORSPEC_CKEN/PEREN/HCKEN/IPGEN, these are reserved bits. Instead, use VENDORSPEC_FRC_SDCLK_ON to gate on/off the card clock output. After commit b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support"), we meet SD3.0 card can't work at UHS mode, mmc_switch_voltage() fail because the second mmc_wait_dat0 return -ETIMEDOUT. According to SD spec, during voltage switch, need to gate off/on the card clock. If not set the FRC_SDCLK_ON, after CMD11, hardware will gate off the card clock automatically, so card do not detect the clock off/on behavior, so will draw the data0 line low until next command. Fixes: b5874b552ffa ("mmc: fsl_esdhc_imx: add wait_dat0() support") Tested-by: Tim Harvey <tharvey@gateworks.com> Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
* | mmc: mvebu: convert to driver modelHarm Berntsen2021-04-082-126/+190
|/ | | | | | | | | | | | | | | | | This is a straightforward conversion of the old, non-dm driver. It was done in-place as the deadline for non-dm MMC has passed. Previous commits ensured that no board depends on the old, non-dm variant. Tested on a Kirkwood based board with eMMC. Signed-off-by: Harm Berntsen <harm.berntsen@nedap.com> Tested-by: Harm Berntsen <harm.berntsen@nedap.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Stefan Roese <sr@denx.de> CC: Pantelis Antoniou <panto@antoniou-consulting.com> CC: Stefan Roese <sr@denx.de> CC: Gerald Kerma <drEagle@doukki.net> CC: Simon Glass <sjg@chromium.org> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: mmc-uclass: Use dev_seq() to read aliases node's indexAswath Govindraju2021-04-061-7/+5
| | | | | | | | | Use dev_seq() to read aliases node's index and pass it as device number for creating bulk device. Suggested-by: Grygorii Strashko <grygorii.strashko@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: Check for device with a seq number equal to num before checking against ↵Aswath Govindraju2021-04-061-3/+5
| | | | | | | | | | | index First check if there is an alias for the device tree node defined with the given num before checking against device index. Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Lokesh Vutla <lokeshvutla@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: fsl_esdhc: add pulse width detection workaroundMichael Walle2021-04-062-1/+8
| | | | | | | | | | | HS400 mode on the LS1028A SoC isn't reliable. The linux driver has a workaroung for the pulse width detection. Apply this workaround in u-boot, too. This will make HS400 mode work reliably on the LS1028A SoC. Signed-off-by: Michael Walle <michael@walle.cc> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: fsl_esdhc: add workaround for erratum A-011334Michael Walle2021-04-062-1/+27
| | | | | | | LS1028A SoCs are restricted in what divider values are allowed for HS400 mode. This is basically a port from the corresponding linux driver. Signed-off-by: Michael Walle <michael@walle.cc>
* Merge tag 'v2021.04-rc5' into nextTom Rini2021-03-291-1/+2
|\ | | | | | | Prepare v2021.04-rc5
| * mmc: mtk-sd: don't ignore max-frequency from device treeDaniel Golle2021-03-171-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | commit e58e68d9 ("mmc: mtk-sd: assign plat->cfg.f_max with a correct value") wrongly assumed that plat->cfg.f_max is always unset at the time mscd_drv_probe() is run. This is not true in case max-frequency being defined in device tree, as it is then already set by mmc_of_parse() in msdc_of_to_plat(). Only set plat->cfg.f_max to the default maximum value in case it is not already set to a sane value. Fixes: e58e68d93e ("mmc: mtk-sd: assign plat->cfg.f_max with a correct value") Cc: Stefan Roese <sr@denx.de> Cc: Weijie Gao <weijie.gao@mediatek.com> Signed-off-by: Daniel Golle <daniel@makrotopia.org>
* | mmc: pci_mmc: Set up the card detectSimon Glass2021-03-271-1/+5
| | | | | | | | | | | | | | The driver currently reads the card-detect but does not register it with the MMC stack. Update this so that card-detect works as expected. Signed-off-by: Simon Glass <sjg@chromium.org>
* | dm: Rename device_get_by_driver_info_idx()Simon Glass2021-03-261-2/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This function finds a device by its driver_info index. With of-platdata-inst we do not use driver_info, but instead instantiate udevice records at build-time. However the semantics of using the function are the same in each case: the caller provides an index and gets back a device. So rename the function to device_get_by_ofplat_idx(), so that it can be used for both situations. The caller does not really need to worry about the details. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Simon Glass <sjg@chromium.org>
* | mmc: pci: Fix Kconfig dependencyBin Meng2021-03-221-0/+1
|/ | | | | | | | The PCI MMC driver depends on the generic MMC SDHCI driver, otherwise it does not compile. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* Merge tag 'u-boot-imx-20210303' of ↵Tom Rini2021-03-031-0/+7
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2021.04 ---------------- - new boards: - i.MX8MN Beacon EmbeddedWorks (2GB) - Gateworks Venice imx8mm - convert to DM: - imx53-qsb, mx53loco, mx51evk, mx23-evk - Fixes : - Network : FEC ethernet quirks - DH dh-imx6 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6597
| * mmc: fsl_esdhc_imx: fix the DTOCV to 0xEHaibo Chen2021-03-011-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | On imx6Q/imx6DL, we find if config the DTOCV to 0~3, it will impact cmd6 behavior, after cmd6 get transfer complete interrupt, the data0 line will keep low over 5 seconds. This should be a IC bug on imx6Q/DL. For other platforms, do not has this issue. To fix this issue, fix the DTOCV to 0xE, the max setting, this also align with Linux configuration. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: fsl_esdhc_imx: Add a compatible for i.MX51Fabio Estevam2021-03-011-0/+1
| | | | | | | | | | | | | | | | Add a compatible for i.MX51 so that i.MX51 can use this driver via driver model. Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | drivers: mmc: iproc_sdhci: enable HS200 modeBharat Gooty2021-03-021-9/+83
|/ | | | | | | | | | Add tuning functionality which is needed for HS200 mode. For HS200, program the correct needed 1.8 voltage Signed-off-by: Bharat Gooty <bharat.gooty@broadcom.com> Signed-off-by: Rayagonda Kokatanur <rayagonda.kokatanur@broadcom.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* mmc: sandbox: Add support for writingSean Anderson2021-02-261-6/+37
| | | | | | | | | | This adds support writing to the sandbox mmc backed by an in-memory buffer. The unit test has been updated to test reading, writing, and erasing. I'm not sure what MMCs erase to; I picked 0, but if it's 0xFF then that can be easily changed. Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Merge tag 'xilinx-for-v2021.04-rc3' of ↵Tom Rini2021-02-231-1/+1
|\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-microblaze Xilinx changes for v2021.04-rc3 qspi: - Support for dual/quad mode - Fix speed handling clk: - Add clock enable function for zynq/zynqmp/versal gem: - Enable clock for Versal - Fix error path - Fix mdio deregistration path fpga: - Fix buffer alignment for ZynqMP xilinx: - Fix reset reason clearing in ZynqMP - Show silicon version in SPL for Zynq/ZynqMP - Fix DTB selection for ZynqMP - Rename zc1275 to zcu1275 to match DT name
| * clk: zynq: Add dummy clock enable functionMichal Simek2021-02-231-1/+1
| | | | | | | | | | | | | | | | | | A lot of Xilinx drivers are checking -ENOSYS which means that clock driver doesn't have enable function. Remove this checking from drivers and create dummy enable function as was done for clk_fixed_rate driver by commit 6bf6d81c1112 ("clk: fixed_rate: add dummy enable() function"). Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* | mmc: rockchip_dw_mmc: use mmc_pwrseq instead of rockchip_mmc_pwrseqJaehoon Chung2021-02-191-39/+3
| | | | | | | | | | | | Use mmc_pwrseq instead of rockchip_mmc_pwrseq. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: meson_gx_mmc: use mmc_pwrseq instead of meson_mmc_pwrseqJaehoon Chung2021-02-191-42/+3
| | | | | | | | | | | | | | Use mmc_pwrseq instead of meson_mmc_pwrseq. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Acked-by: Neil Armstrong <narmstrong@baylibre.com>
* | mmc: pwrseq: add mmc-pwrseq file to provide a generic interfaceJaehoon Chung2021-02-193-0/+59
| | | | | | | | | | | | Add mmc-pwrseq file to provide a generic interface. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: mmc_spi: Document the 3 local functionsBin Meng2021-02-191-1/+35
| | | | | | | | | | | | | | | | | | mmc_spi_sendcmd(), mmc_spi_readdata() and mmc_spi_writedata() are currently undocumented. Add comment blocks to explain the arguments and the return value. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: mmc_spi: Fix potential spec violation in receiving card responseBin Meng2021-02-191-15/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After command is sent and before card response shows up on the line, there is a variable number of clock cycles in between called Ncr. The spec [1] says the minimum is 1 byte and the maximum is 8 bytes. Current logic in mmc_spi_sendcmd() has a flaw that it could only work with certain SD cards with their Ncr being just 1 byte. When resp_match is false, the codes try to receive only 1 byte from the SD card. On the other hand when resp_match is true, the logic happens to be no problem as it loops until timeout to receive as many bytes as possible to see a match of the expected resp_match_value. However not every call to mmc_spi_sendcmd() is made with resp_match being true hence this exposes a potential issue with SD cards that have a larger Ncr value. Given no issue was reported as of today, we can reasonably conclude that all cards being used on the supported boards happen to have a 1 byte Ncr timing requirement. But a broken case can be triggered by utilizing QEMU to emulate a larger value of Ncr (by default 1 byte Ncr is used on QEMU). This commit fixes such potential spec violation to improve the card compatibility. [1] "Physical Layer Specification Version 8.00" chapter 7.5.1: Command / Response chapter 7.5.4: Timing Values Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: mmc_spi: Move argument check to the beginning of mmc_spi_sendcmd()Bin Meng2021-02-191-3/+3
| | | | | | | | | | | | | | The argument check should happen before any transfer on the SPI lines. Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: mmc_spi: Print verbose debug output when crc16 check failsBin Meng2021-02-191-2/+4
| | | | | | | | | | | | | | Add some verbose debug output when crc16 check fails. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: fix response timeout after switch commandStefan Bosch2021-02-191-1/+2
| | | | | | | | | | | | | | | | | | After issuing the switch command: Wait until 'current state' of the card status becomes 'tran'. This prevents from response timeout at the next command because of 'current state' = 'data'. Signed-off-by: Stefan Bosch <stefan_b@posteo.net> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: sdhci: skip cache invalidation if DMA is not usedYuezhang.Mo@sony.com2021-02-191-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | If DMA(SDMA or ADMA) is not used, the cache invalidation after reading is no need, should be skipped. Otherwise U-Boot may hang at the cache invalidation. Found this issue and tested this fix on DragonBoard 410c. Fixes: commit 4155ad9aac94 ("mmc: sdhci: fix missing cache invalidation after reading by DMA") Signed-off-by: Yuezhang.Mo <Yuezhang.Mo@sony.com> Reviewed-by: Andy Wu <Andy.Wu@sony.com>
* | mmc: initialize an err variableJaehoon Chung2021-02-191-1/+1
| | | | | | | | | | | | | | | | Initialize an err variable to 0. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reported-by: Coverity (CID: 313548) Reviewed-by: Tom Rini <trini@konsulko.com>
* | mmc: Introduce mmc_phys_to_bus()/mmc_bus_to_phys()Nicolas Saenz Julienne2021-02-181-4/+6
| | | | | | | | | | | | | | | | | | | | This will allow us to use DM variants of phys_to_bus()/bus_to_phys() when relevant. Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Matthias Brugger <mbrugger@suse.com>
* | Merge branch '2021-02-02-drop-asm_global_data-when-unused'Tom Rini2021-02-1523-0/+24
|\ \ | | | | | | | | | - Merge the patch to take <asm/global_data.h> out of <common.h>
| * | common: Drop asm/global_data.h from common headerSimon Glass2021-02-0223-0/+24
| |/ | | | | | | | | | | | | | | | | | | | | | | Move this out of the common header and include it only where needed. In a number of cases this requires adding "struct udevice;" to avoid adding another large header or in other cases replacing / adding missing header files that had been pulled in, very indirectly. Finally, we have a few cases where we did not need to include <asm/global_data.h> at all, so remove that include. Signed-off-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Rini <trini@konsulko.com>
* | mmc: mv_sdhci: parse device-tree entryBaruch Siach2021-02-081-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Call mmc_of_parse() so that generic DT properties like 'non-removable' are taken into account. This fixes boot on Clearfog with eMMC on SOM that requires the non-removable property. Reported-by: Thorsten Spille <thorsten_spille@netcor.de> Signed-off-by: Baruch Siach <baruch@tkos.co.il> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
* | mmc: am654_sdhci: Use sdhci_set_control_reg()Faiz Abbas2021-02-041-16/+2
| | | | | | | | | | | | | | | | | | Use the generic sdhci_set_control_reg() instead of duplicating in platform driver. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: am654_sdhci: Fix HISPD bit configuration in some lower speed modesFaiz Abbas2021-02-042-2/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | According to the AM654x Data Manual[1], the setup timing in lower speed modes can only be met if the controller uses a falling edge data launch. To ensure this, the HIGH_SPEED_ENA (HOST_CONTROL[2]) bit should be cleared in default speed, SD high speed, MMC high speed, SDR12 and SDR25 speed modes. Use the sdhci writeb callback to implement this condition. [1] http://www.ti.com/lit/gpn/am6546 Section 5.10.5.16.1 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: am654_sdhci: Add support for software tuningFaiz Abbas2021-02-041-0/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new SW tuning App note[1], a custom tuning algorithm is required for eMMC HS200, HS400 and SD card UHS modes. The algorithm involves running through the 32 possible input tap delay values and sending the appropriate tuning command (CMD19/21) for each of them to get a fail or pass result for each of the values. Typically, the range will have a small contiguous failing window. Considering the tuning range as a circular buffer, the algorithm then sets a final tuned value directly opposite to the failing window. [1] https://www.ti.com/lit/pdf/spract9 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: am654_sdhci: Add support for writing to clkbuf_selFaiz Abbas2021-02-041-0/+11
| | | | | | | | | | | | | | | | | | Add support for writing new clock buffer select property for both the am654x and j721e 4 bit IPs Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: am654_sdhci: Add support for input tap delayFaiz Abbas2021-02-041-80/+161
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | DLL need only be enabled for speed modes and clock frequencies at or above 50 MHz. For speed modes that don't enable the DLL, we need to configure a static input delay value. This involves reading an optional itap-del-sel-* value from the device tree and configuring it for the appropriate speed mode. Therefore, move all dll configurations to their own functions and gate it with 50 MHz speed and a minimum mode. If both these conditions are not satisfied then configure delay chain modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: am654_sdhci: Add support for AM65x SR2.0Faiz Abbas2021-02-041-0/+30
| | | | | | | | | | | | | | | | | | Add Support for AM65x PG2.0. Use the SoC bus framework to fixup the platform data and do DLL calibration if the revision is 1.0 Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: am654_sdhci: Add flag for PHY calibrationFaiz Abbas2021-02-041-12/+14
| | | | | | | | | | | | | | | | | | | | | | | | Not all controllers need calibration for the PHY DLL. Add a DLL_CALIB flag to indicate the same. Also move the write of trm_icp and driver strength to the set_clock() function to match the kernel configuration flow. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: am654_sdhci: Convert flag fields to BIT macroFaiz Abbas2021-02-041-4/+4
| | | | | | | | | | | | | | | | Convert the flags field defines to use the BIT() macro. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: am654_sdhci: Unconditionally switch off DLL in the beginning of ios_post()Faiz Abbas2021-02-041-9/+1
| | | | | | | | | | | | | | | | | | | | | | | | There are some speed modes that work without switching the dll on. Unconditionally switch off the DLL before setting clock frequency to support this case. The software will automatically enable DLL for speed modes that require it. This also means the dll_on priv data member is no longer required. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: sdhci: Add helper functions for UHS modesFaiz Abbas2021-02-041-0/+95
|/ | | | | | | | | Add a set_voltage() function which handles the switch from 3.3V to 1.8V for SD card UHS modes. Signed-off-by: Faiz Abbas <faiz_abbas@ti.com> Signed-off-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
generated by cgit (git 2.34.1) at 2025-06-13 14:49:56 +0000