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* Merge tag 'u-boot-atmel-fixes-2021.01-b' of ↵Tom Rini2020-12-111-1/+2
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel Second set of u-boot-atmel fixes for 2021.01 cycle This set includes very important fixes for: MMC booting on several boards, drive strength on sam9x60ek mmc lines, compile issues for timer.c old driver, removal of unwanted access to sam9x60 bit for oscillator bypass mode, and eeproms read on sama5d2_icp.
| * mmc: atmel-sdhci: fix the clk_enable call in case of no opsEugen Hristev2020-11-261-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | If the clock driver does not offer a clk_enable ops, then the system will return -ENOSYS. The clk_enable works with CCF (common clock framework). Some clocks in some cases (like the generic clock for some products: sama5d2) do not have the clk_enable primitive, and in this case probing of the driver will fail. This patch changes the behavior to return an error in case there is really an error, and not a missing primitive. If the clock driver does not have an enable primitive, most likely clocks are always enabled or enabled in the set_rate primitives. Fixes: 81f16438d4 ("mmc: atmel-sdhci: enable the required generic clock") Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | Merge tag 'u-boot-stm32-20201209' of ↵Tom Rini2020-12-092-2/+2
|\ \ | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-stm - Manage CONFIG_ENV_EXT4_DEVICE_AND_PART in stm32mp1 board - Update ARM STI and ARM STM STM32MP Arch maintainers emails - Enable internal pull-ups for SDMMC1 on DHCOM SoM
| * | treewide: Update email address Patrick Delaunay and Patrice ChotardPatrice Chotard2020-12-092-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Update Patrick and my email address with the one dedicated to upstream activities. Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com>
* | | mmc: fsl_esdhc_imx: optimize the timing settingHaibo Chen2020-12-061-8/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For imx usdhc/esdhc, once set the DDR_EN, enable the DDR mode, the card clock will be divied by 2 automatically by the host. So need to first config the DDR_EN correctly, then update the card clock. This will make sure the actual card clock is as our expected. IC also suggest config the DDR_EN firstly, then config the clock divider. For HS400/HS400ES mode, need to config the strobe dll, this need to based on the correct target clock rate, so need to do this after clock rate is update. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | | mmc: fsl_esdhc_imx: add wait_dat0() supportHaibo Chen2020-12-061-0/+15
|/ / | | | | | | | | | | | | Add wait_dat0() support, upper layer will use this callback. Signed-off-by: Haibo Chen <haibo.chen@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: check a return value about regulator's always-onJaehoon Chung2020-11-281-2/+2
| | | | | | | | | | | | | | | | | | Regulator can be set to "always-on". It's not error about enable/disable. It needs to check about its condition. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | mmc: display an error number to debugJaehoon Chung2020-11-281-5/+5
| | | | | | | | | | | | | | It's useful to know an error number when it's debugging. Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | mmc: fsl_esdhc: make sure delay chain locked for HS400Yangbo Lu2020-11-281-3/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For eMMC HS400 mode, the DLL reset is a required step for mmc rescan. This step has not been documented in reference manual, but the RM will be fixed sooner or later. In previous commit to support eMMC HS400, db8f936 mmc: fsl_esdhc: support eMMC HS400 mode the steps to configure DLL could be found in commit message, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. these would be fixed as, 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 13.1 Write DLLCFG0[DLL_RESET] to 1 and wait for 1us, then write DLLCFG0[DLL_RESET] 14. Wait for delay chain to lock. This patch is to add the step of DLL reset, and make sure delay chain locked for HS400. Fixes: db8f93672b42 ("mmc: fsl_esdhc: support eMMC HS400 mode") Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: fsl_esdhc: set sysctl register for clock initializationYangbo Lu2020-11-281-1/+1
| | | | | | | | | | | | | | | | | | The initial clock setting should be through sysctl register only, while the mmc_set_clock() will call mmc_set_ios() introduce other configurations like bus width, mode, and so on. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: Add some helper functions for retrying on errorSean Anderson2020-11-281-83/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | All of the existing quirks add retries to various calls of mmc_send_cmd. mmc_send_cmd_quirks is a helper function to do this retrying behavior. It checks if quirks mode is enabled, and if a specific quirk is activated it retries on error. This also adds mmc_send_cmd_retry, which retries on error every time (instead of if a quirk is activated). Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: meson-gx: change clock phase value on SM1 SoCsNeil Armstrong2020-11-122-4/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Amlogic SM1 SoCs doesn't work over 50MHz. When phase sets to 270', it's working fine over 50MHz on Amlogic SM1 SoCs. Since Other Amlogic SoCs doens't report an issue, phase value is using to 180' by default. To distinguish which value is used adds an u-boot only sm1 compatible. In future, it needs to find what value is a proper about each SoCs. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com> Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com> Tested-by: Anand Moon <linux.amoon@gmail.com>
* | mmc: meson-gx: move arch header to local headerNeil Armstrong2020-11-122-1/+90
|/ | | | | | | Move the asm/arch-meson/sd_emmc.h to a local meson_gx_mmc.h, remove the useless if/then and fix the meson_gx_mmc.c include. Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
* Merge tag 'dm-pull-30oct20' of ↵Tom Rini2020-10-301-5/+2
|\ | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-dm of-platdata and dtoc improvements sandbox SPL tests binman support for compressed sections
| * dm: Use driver_info index instead of pointerSimon Glass2020-10-291-5/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present we use a 'node' pointer in the of-platadata phandle_n_arg structs. This is a pointer to the struct driver_info for a particular device, and we can use it to obtain the struct udevice pointer itself. Since we don't know the struct udevice pointer until it is allocated in memory, we have to fix up the phandle_n_arg.node at runtime. This is annoying since it requires that SPL's data is writable and adds a small amount of extra (generated) code in the dm_populate_phandle_data() function. Now that we can find a driver_info by its index, it is easier to put the index in the phandle_n_arg structures. Update dtoc to do this, add a new device_get_by_driver_info_idx() to look up a device by drive_info index and update the tests to match. Signed-off-by: Simon Glass <sjg@chromium.org>
* | mmc: zynq_sdhci: Extend UHS timings till hs200Ashok Reddy Soma2020-10-291-1/+1
| | | | | | | | | | | | | | | | | | Fix the condition to set UHS timings for speeds upto HS200. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: zynq_sdhci: Add clock phase delays for VersalAshok Reddy Soma2020-10-271-4/+156
| | | | | | | | | | | | | | | | | | | | | | Define default values for input and output clock phase delays for Versal. Also define functions for setting tapdelays based on these clock phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: zynq_sdhci: Set tapdelays based on clk phase delaysAshok Reddy Soma2020-10-271-5/+123
| | | | | | | | | | | | | | | | | | | | | | Define and use functions for setting input and output tapdelays based on clk phase delays. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: zynq_sdhci: Read clock phase delays from dtMichal Simek2020-10-271-0/+85
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define input and output clock phase delays with pre-defined values. Define arasan_sdhci_clk_data type structure and add it to priv structure and store these clock phase delays in it. Read input and output clock phase delays from dt. If these values are not passed through dt, use pre-defined values. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: zynq_sdhci: Move macro to the topMichal Simek2020-10-271-2/+2
| | | | | | | | | | | | | | | | | | | | Just group macros below headers. Other patches will be using this location too. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: Define timing macro'sAshok Reddy Soma2020-10-271-13/+11
| | | | | | | | | | | | | | | | | | | | Define timing macro's for all the available speeds of mmc. This is done similar to linux. Replace speed macro's used with these new timing macro's wherever applicable. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* | Revert "mmc: zynq: parse dt when probing"Ashok Reddy Soma2020-10-272-1/+7
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 942b5fc03218d1c94468fc658e7dec65dabcc830. This is partial revert of the above commit. mmc_of_parse() is reading no-1-8-v from device tree and if set, it is clearing the UHS speed capabilities of cfg->host_caps. cfg->host_caps &= ~(UHS_CAPS | MMC_MODE_HS200 | MMC_MODE_HS400 | MMC_MODE_HS400_ES); This is still missing to clear UHS speeds like SDHCI_SUPPORT_SDR104, SDHCI_SUPPORT_SDR50 and SDHCI_SUPPORT_DDR50. Even if we clear the flags SDHCI_SUPPORT_XXX in mmc_of_parse(), these speed flags are getting set again in cfg->host_caps in sdhci_setup_cfg(). The reason for this is, SDHCI_SUPPORT_XXX flags are cleared only if controller is not capable of supporting MMC_VDD_165_195 volts. if (caps & SDHCI_CAN_VDD_180) cfg->voltages |= MMC_VDD_165_195; if (!(cfg->voltages & MMC_VDD_165_195)) caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 | SDHCI_SUPPORT_DDR50); It means "no-1-8-v", which is read from DT is not coming in to effect. So it is better we keep the host quirks(SDHCI_QUIRK_NO_1_8_V) to clear UHS speeds based on no-1-8-v from device tree. Hence revert the functionality related to no-1-8-v only, rest is fine in the patch. Signed-off-by: Ashok Reddy Soma <ashok.reddy.soma@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* mmc: mtk-sd: change some dev_err into dev_dbgFabien Parent2020-10-221-3/+3
| | | | | | | | dev_err has been used for debugging and a few dev_err message are printed for normal code execution. Make them dev_dbg instead. Signed-off-by: Fabien Parent <fparent@baylibre.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
* mmc: Fix comment typoNaoki Hayama2020-10-221-1/+1
| | | | | | %s/occured/occurred/ Signed-off-by: Naoki Hayama <naoki.hayama@lineo.co.jp>
* mmc: stm32_sdmmc2: Use mmc_of_parse() to read host capabilitiesAlexandru Gagniuc2020-10-211-16/+2
| | | | | | | | | | | mmc_of_parse() can populate the 'f_max' and 'host_caps' fields of struct mmc_config from devicetree. The same logic is duplicated in stm32_sdmmc2_probe(). Use mmc_of_parse(), which is more generic. Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* mmc: mmc_of_parse: Enable 52 MHz support with "cap-mmc-highspeed"Alexandru Gagniuc2020-10-211-1/+1
| | | | | | | | | | | | | | | | "cap-mmc-highspeed" enables support for 26 MHz MMC, but there is no additional flag to enable 52 MHz MMC. In Linux. "cap-mmc-highspeed" is used for MMC HS at both 26MHz and 52MHz. Use the same approach and enable MMC_CAP(MMC_HS_52) host capability when "cap-mmc-highspeed" is found in the devicetree. In the event an MMC card doesn't support 52 MHz, it will be clocked at a speed based on its EXT CSD, even on 52 MHz host controllers Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@st.com> Tested-by: Patrick Delaunay <patrick.delaunay@st.com> Reviewed-by: Patrice Chotard <patrice.chotard@st.com>
* mmc: octeontx_hsmmc.c: Remove test debug messageStefan Roese2020-10-161-1/+0
| | | | | | | | | | Remove a left-over debug test message from the Octeon TX / TX2 MMC driver. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Aaron Williams <awilliams@marvell.com> Cc: Suneel Garapati <sgarapati@marvell.com> Cc: Chandrakala Chavva <cchavva@marvell.com>
* Merge tag 'mmc-2020-10-14' of ↵Tom Rini2020-10-159-229/+482
|\ | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-mmc - fsl_esdhc_imx cleanup - not send cm13 if send_status is 0. - Add reinit API - Add mmc HS400 for fsl_esdhc - Several cleanup for fsl_esdhc - Add ADMA2 for sdhci
| * mmc: fsl_esdhc: add ADMA2 supportMichael Walle2020-10-142-5/+53
| | | | | | | | | | | | | | | | | | | | | | Newer eSDHC controllers support ADMA2 descriptor tables which support 64bit DMA addresses. One notable user of addresses in the upper memory segment is the EFI loader. If support is enabled, but the controller doesn't support ADMA2, we will fall back to SDMA (and thus 32 bit DMA addresses only). Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc: replace most #ifdefs by IS_ENABLED()Michael Walle2020-10-141-73/+65
| | | | | | | | | | | | | | Make the code cleaner and drop the old-style #ifdef constructs where it is possible. Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc_imx: replace all readl/writel to esdhc_read32/esdhc_write32Haibo Chen2020-10-121-32/+32
| | | | | | | | | | | | | | Currently, readl/writel and esdhc_read32/esdhc_write32 are used. To align the usage, change to only use esdhc_read32/esdhc_write32. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * mmc: do not check argument of free() beforehandHeinrich Schuchardt2020-10-121-2/+1
| | | | | | | | | | | | free() checks if its argument in NULL. No need to check it twice. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * mmc: sdhci: move the ADMA2 table handling into own moduleMichael Walle2020-10-124-55/+87
| | | | | | | | | | | | | | | | There are other (non-SDHCI) controllers which supports ADMA2 descriptor tables, namely the Freescale eSDHC. Instead of copying the code, move it into an own module. Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc: simplify esdhc_setup_data()Michael Walle2020-10-121-27/+42
| | | | | | | | | | | | | | | | First, we need the waterlevel setting for PIO mode only. Secondy, both DMA setup code is identical for both directions, except for the data pointer. Thus, unify them. Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc: use dma-mapping APIMichael Walle2020-10-121-35/+14
| | | | | | | | | | | | | | Use the dma_{map,unmap}_single() calls. These will take care of the flushing and invalidation of caches. Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc: simplify 64bit check for SDMA transfersMichael Walle2020-10-121-23/+6
| | | | | | | | | | | | | | | | | | | | SDMA can only do DMA with 32 bit addresses. This is true for all architectures (just doesn't apply to 32 bit ones). Simplify the code and remove unnecessary CONFIG_FSL_LAYERSCAPE. Also make the error message more concise. Signed-off-by: Michael Walle <michael@walle.cc>
| * mmc: fsl_esdhc_imx: remove the 1ms delay before sending commandHaibo Chen2020-10-121-7/+0
| | | | | | | | | | | | | | | | | | | | | | This 1ms delay before sending command already exist from the beginning of the fsl_esdhc driver added in year 2008. Now this driver has been split for two files: fsl_esdhc.c and fsl_esdhc_imx.c. fsl_esdhc_imx.c only for i.MX series. i.MX series esdhc/usdhc do not need this 1ms delay before sending any command. So remove this 1ms, this will save a lot time if handling a large mmc data. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * mmc: do not send cmd13 if the parameter 'send_status' is 0 for __mmc_switchHaibo Chen2020-10-121-1/+3
| | | | | | | | | | | | | | | | According to the code logic in __mmc_switch, if the parameter 'send_status' is zero, no need to send cmd13, just wait the stated timeout time, then can return directly. Signed-off-by: Haibo Chen <haibo.chen@nxp.com>
| * mmc: fsl_esdhc: fix eMMC HS400 stability issueYangbo Lu2020-10-121-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There was a fix-up for eMMC HS400 stability issue in Linux. Patch link: https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/ commit/?id=58d0bf843b49fa99588ac9f85178bd8dfd651b53 Description: Currently only LX2160A eSDHC supports eMMC HS400. According to a large number of tests, eMMC HS400 failed to work at 150MHz, and for a few boards failed to work at 175MHz. But eMMC HS400 worked fine on 200MHz. We hadn't found the root cause but setting eSDHC_DLLCFG0[DLL_FREQ_SEL] = 0 using slow delay chain seemed to resovle this issue. Let's use this as fixup for now. Introduce the fix-up in u-boot since the issue could be reproduced in u-boot too. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: fix mmc->clock with actual clockYangbo Lu2020-10-121-0/+3
| | | | | | | | | | | | | | | | Fix mmc->clock with actual clock which is divided by the controller, and record it with priv->clock which was removed accidentally. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: support eMMC HS400 modeYangbo Lu2020-10-121-34/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The process for eMMC HS400 mode for eSDHC is, 1. Perform the Tuning Process at the HS400 target operating frequency. Latched the clock division value. 2. if read transaction, then set the SDTIMNGCTL[FLW_CTL_BG]. 3. Switch to High Speed mode and then set the card clock frequency to a value not greater than 52Mhz 4. Clear TBCTL[TB_EN],tuning block enable bit. 5. Change to 8 bit DDR Mode 6. Switch the card to HS400 mode. 7. Set TBCTL[TB_EN], tuning block enable bit. 8. Clear SYSCTL[SDCLKEN] 9. Wait for PRSSTAT[SDSTB] to be set 10. Change the clock division to latched value.Set TBCTL[HS 400 mode] and Set SDCLKCTL[CMD_CLK_CTRL] 11. Set SYSCTL[SDCLKEN] 12. Wait for PRSSTAT[SDSTB] to be set 13. Set DLLCFG0[DLL_ENABLE] and DLLCFG0[DLL_FREQ_SEL]. 14. Wait for delay chain to lock. 15. Set TBCTL[HS400_WNDW_ADJUST] 16. Again clear SYSCTL[SDCLKEN] 17. Wait for PRSSTAT[SDSTB] to be set 18. Set ESDHCCTL[FAF] 19. Wait for ESDHCCTL[FAF] to be cleared 20. Set SYSCTL[SDCLKEN] 21. Wait for PRSSTAT[SDSTB] to be set. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: add a mmc_hs400_prepare_ddr() interfaceYangbo Lu2020-10-122-0/+19
| | | | | | | | | | | | | | | | Add a mmc_hs400_prepare_ddr() interface for controllers which needs preparation before switching to DDR mode for HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: add a hs400_tuning flagYangbo Lu2020-10-121-0/+2
| | | | | | | | | | | | | | | | | | | | | | Some controllers may have difference between HS200 tuning and HS400 tuning, such as different registers setting, different procedure, or different errata. This patch is to add a hs400_tuning flag to identify the tuning for HS400 mode. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: clean TBCTL[TB_EN] manually during initYangbo Lu2020-10-121-0/+3
| | | | | | | | | | | | | | Clean TBCTL[TB_EN] manually during init since it is not able to be reset by reset all operation. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: support tuning for eMMC HS200Yangbo Lu2020-10-121-3/+103
| | | | | | | | | | | | Support tuning process for eMMC HS200 for eSDHC. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com>
| * mmc: fsl_esdhc: add a reinit() callbackYangbo Lu2020-10-121-0/+9
| | | | | | | | | | | | | | Add a reinit() callback for mmc rescan. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
| * mmc: add a reinit() APIYangbo Lu2020-10-122-2/+21
| | | | | | | | | | | | | | | | For DM_MMC, the controller re-initialization is needed to clear old configuration for mmc rescan. Signed-off-by: Yangbo Lu <yangbo.lu@nxp.com> Reviewed-by: Jaehoon Chung <jh80.chung@samsung.com>
* | mmc: remove duplicate mmc_get_env_dev() implementationsDavid Woodhouse2020-10-141-0/+9
|/ | | | | | | Since it's so trivial I could just about tolerate this when there were only two copies of it. But now there are about to be three. Signed-off-by: David Woodhouse <dwmw2@infradead.org>
* Merge branch 'next'Tom Rini2020-10-054-32/+41
|\ | | | | | | | | | | | | Bring in the assorted changes that have been staged in the 'next' branch prior to release. Signed-off-by: Tom Rini <trini@konsulko.com>
| * Merge tag 'u-boot-atmel-2021.01-a' of ↵Tom Rini2020-10-051-3/+10
| |\ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-atmel into next First set of u-boot-atmel features for 2021.01 cycle: This feature set includes a new CPU driver for at91 family, new driver for PIT64B hardware timer, support for new at91 family SoC named sama7g5 which adds: clock support, including conversion of the clock tree to CCF; SoC support in mach-at91, pinctrl and mmc drivers update. The feature set also includes updates for mmc driver and some other minor fixes and features regarding building without the old Atmel PIT and the possibility to read a secondary MAC address from a second i2c EEPROM.
generated by cgit (git 2.34.1) at 2024-11-16 12:15:52 +0000