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* misc: make CONFIG_IRQ selectable for all platformsWasim Khan2021-04-201-3/+2
| | | | | | | | | UCLASS_IRQ driver is not Intel specific. Make CONFIG_IRQ selectable for all platforms. Signed-off-by: Wasim Khan <wasim.khan@nxp.com> Tested-by: Vladimir Oltean <vladimir.oltean@nxp.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* qemu: add MMIO driver for QFWAsherah Connor2021-04-121-0/+7
| | | | | | | | | | Add MMIO driver for QFW. Note that there is no consumer as of this patch. Signed-off-by: Asherah Connor <ashe@kivikakk.ee> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: move QFW to its own uclassAsherah Connor2021-04-121-2/+9
| | | | | | | | | | | | | We move qfw into its own uclass and split the PIO functions into a specific driver for that uclass. The PIO driver is selected in the qemu-x86 board config (this covers x86 and x86_64). include/qfw.h is cleaned up and documentation added. Signed-off-by: Asherah Connor <ashe@kivikakk.ee> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com>
* test: Move some test drivers into their own fileSimon Glass2021-01-051-0/+9
| | | | | | | | | | | At present several test drivers are part of the test file itself. Some of these are useful for of-platdata tests. Separate them out so we can use them for other things also. A few adjustments are needed so this driver can build for sandbox_spl as well. Signed-off-by: Simon Glass <sjg@chromium.org>
* xilinx: common: Move ZYNQ_GEM_I2C_MAC_OFFSET to board KconfigMichal Simek2020-10-271-7/+0
| | | | | | | | | | | | There is no reason to have ZYNQ specific Kconfig macro in generic location to be visible for all other SoCs. That's why move it to Xilinx common location to be visible only for us. Also introduce new bool entry ZYNQ_MAC_IN_EEPROM to have also an option to disable it or enable. This has connection to code which is reading the whole content of i2c and also work with the rest of date not just with MAC address. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* drivers: p2sb: replace Primary-to-Sideband Bus with Primary to Sideband BridgeWolfgang Wallner2020-07-171-6/+6
| | | | | | | | | In Intel's documentation the term P2SB stands for "Primary to Sideband Bridge". Signed-off-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* misc: add driver for the SiFive otp controllerPragnesh Patel2020-06-041-0/+7
| | | | | | | | | | Added a misc driver to handle OTP memory in SiFive SoCs. Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Tested-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com> Tested-by: Jagan Teki <jagan@amarulasolutions.com>
* rename symbol: CONFIG_STM32 -> CONFIG_ARCH_STM32Trevor Woerner2020-05-151-1/+1
| | | | | | Have this symbol follow the pattern of all other such symbols. Signed-off-by: Trevor Woerner <twoerner@gmail.com>
* misc: pmic_esm: Add support for PMIC ESM driverTero Kristo2020-03-031-0/+7
| | | | | | | | | | | The ESM (Error Signal Monitor) is used on certain PMIC versions to handle error signals propagating from rest of the system. If these reach the PMIC, it is typically a last resort fatal error which requires a system reset. The ESM driver does the proper configuration for the ESM module to reach this end goal. Initially, only TPS65941 PMIC is supported for this. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* misc: k3_esm: Add support for Texas Instruments K3 ESM driverTero Kristo2020-03-031-0/+5
| | | | | | | | | | | The ESM (Error Signaling Module) is used to route error signals within the K3 SoCs somewhat similar to interrupts. The handling for these is different though, and can be routed for hardware error handling, to be handled by safety processor or just as error interrupts handled by the main processor. The u-boot level ESM driver is just used to configure the ESM signals so that they get routed to proper destination. Signed-off-by: Tero Kristo <t-kristo@ti.com>
* x86: Move UCLASS_IRQ into a separate fileSimon Glass2019-12-151-0/+9
| | | | | | | | | | | Update this uclass to support the needs of the Apollo Lake ITSS. It supports four operations. Move the uclass into a separate directory so that sandbox can use it too. Add a new Kconfig to control it and enable this on x86. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* pci: Add support for p2sb uclassSimon Glass2019-12-151-0/+33
| | | | | | | | | | | | | The Primary-to-Sideband bus (P2SB) is used to access various peripherals through memory-mapped I/O in a large chunk of PCI space. The space is segmented into different channels and peripherals are accessed by device-specific means within those channels. Devices should be added in the device tree as subnodes of the p2sb. This adds a uclass and enables it for sandbox. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* misc: add driver for the Rockchip otp controllerFinley Xiao2019-11-171-0/+9
| | | | | | | | | Newer Rockchip socs like the px30 use a different ip block to handle one-time-programmable memory, so add a misc driver for it as well. Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com> Signed-off-by: Heiko Stuebner <heiko.stuebner@theobroma-systems.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
* misc: k3_avs: add driver for K3 Adaptive Voltage Scaling Class 0Tero Kristo2019-11-071-0/+9
| | | | | | | | | | Adaptive Voltage Scaling is a technology used in TI SoCs to optimize the operating voltage based on characterization data written to efuse during production. Add a driver to support this feature for K3 line of SoCs, initially for AM65x. Signed-off-by: Tero Kristo <t-kristo@ti.com> Signed-off-by: Keerthy <j-keerthy@ti.com>
* misc: microchip_flexcom: introduce microchip_flexcom driverEugen Hristev2019-10-241-0/+9
| | | | | | | | | | | The Microchip Flexcom is just a wrapper which embeds a SPI controller, an I2C controller and an USART. Only one function can be used at a time and is chosen at boot time according to the device tree. The bindings are kept as in Linux. The driver registers to MISC_UCLASS. Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
* misc: Kconfig: make i.MX7ULP could use MXC_OCOTPPeng Fan2019-10-081-1/+1
| | | | Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Kconfig: Varios: Fix more SPL, TPL dependenciesAdam Ford2019-08-261-0/+2
| | | | | | | | | | | | | | | Several options are presenting themselves on a various boards where the options are clearly not used. (ie, SPL/TPL options when SPL or TPL are not defined) This patch is not attempting to be a complete list of items, but more like low hanging fruit. In some instances, I wasn't sure of DM was required, so I simply made them SPL or TPL. This patch attempts to reduce some of the menuconfig noise by defining dependencies so they don't appear when not used. Signed-off-by: Adam Ford <aford173@gmail.com>
* spl: misc: Allow misc drivers in SPL and TPLSimon Glass2019-05-211-0/+72
| | | | | | | | In some cases it is necessary to read the keyboard in early phases of U-Boot. The cros_ec keyboard is kept in the misc directory. Update the config to allow this. Signed-off-by: Simon Glass <sjg@chromium.org>
* configs: move CONFIG_MXC_OCOTP to KconfigMarcel Ziswiler2019-04-131-0/+2
| | | | | | | | | | | | | | While commit 3e020f03e94f ("driver: misc: add MXC_OCOTP Kconfig entry") introduced a Kconfig entry it did not actually migrate all configurations to using it. As CONFIG_MXC_OCOTP was in mx{6/7}_common.h enable it by default on those architectures. Additionally, also enable it on ARCH_IMX8M and ARCH_VF610 where all current members enabled it through their legacy configuration header files. Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* xilinx: common: Remove !DM_i2C code for reading mac from eepromMichal Simek2019-02-141-0/+1
| | | | | | | | All platforms are converted to DM_I2C that's why there is no reason to keep this code here. Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* misc: Add JZ47xx efuse driverPaul Burton2018-12-191-0/+6
| | | | | | | | | | Add driver for the efuse block in the JZ47xx SOC. Cc: Daniel Schwierzeck <daniel.schwierzeck@gmail.com> Signed-off-by: Paul Burton <paul.burton@imgtec.com> Signed-off-by: Marek Vasut <marek.vasut@gmail.com> Signed-off-by: Ezequiel Garcia <ezequiel@collabora.com> Reviewed-by: Marek Vasut <marex@denx.de>
* misc: Add IHS FPGA driverMario Six2018-11-141-0/+9
| | | | | | | | Add a driver for gdsys IHS (Integrated Hardware Systems) FPGAs, which supports initialization of the FPGA, as well as information gathering. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* misc: Add gdsys_soc driverMario Six2018-11-141-0/+8
| | | | | | | This patch adds a driver for the bus associated with a IHS FPGA. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* misc: Add support for the Arm Versatile Express config busLiviu Dudau2018-10-061-0/+8
| | | | | | | | | | | | Add support for the Arm Versatile Express config bus that is being used for exposing various subsystems via a generic configuration bus. This driver adds support for generating transactions on this configuration bus and can be used by other drivers to abstract the communication with the actual function providers. Signed-off-by: Liviu Dudau <liviu.dudau@foss.arm.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* common: Generic loader for file systemTien Fong Chee2018-09-281-0/+9
| | | | | | | | | This is file system generic loader which can be used to load the file image from the storage into target such as memory. The consumer driver would then use this loader to program whatever, ie. the FPGA device. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* misc: Add MPC83xx serdes driverMario Six2018-09-181-0/+7
| | | | | | | | Add a driver to configure the SerDes (Serializer/Deserializer) lanes on the MPC83xx architecture. Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Mario Six <mario.six@gdsys.cc>
* Convert CONFIG_TWL4030_LED et al to KconfigAdam Ford2018-08-171-0/+5
| | | | | | | | | | | This converts the following to Kconfig: CONFIG_TWL4030_LED CONFIG_TWL4030_INPUT This also removes dead references to: CONFIG_TWL4030_KEYPAD Signed-off-by: Adam Ford <aford173@gmail.com>
* misc: Add gdsys_ioep driverMario Six2018-08-111-0/+6
| | | | | | Add driver for the IHS IO endpoint on IHS FPGAs. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* misc: stm32: Add STM32MP1 supportPatrick Delaunay2018-07-201-1/+1
| | | | | | | | | | | | Following next kernel rcc bindings, we must use a MFD RCC driver which is able to bind both clock and reset drivers. We can reuse and adapt RCC MFD driver already available for MCU SoCs (F4/F7/H7). Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com>
* stm32mp1: add FUSE command supportPatrick Delaunay2018-05-261-0/+9
| | | | | | | | Add support of fuse command (read/write/program/sense) on bank 0 to access to BSEC SAFMEM (4096 OTP bits). Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com>
* gdsys: drivers: Add gdsys_rxaui_ctrl driverMario Six2018-05-081-1/+5
| | | | | | | Add a driver for RXAUI control on IHS FPGAs. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org>
* i2c: Added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSETVipul Kumar2018-03-011-0/+6
| | | | | | | | | This patch added Kconfig support for CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET and enabled it in respective defconfig. Signed-off-by: Vipul Kumar <vipulk@xilinx.com> Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* dm: misc: add stm32 rcc driverChristophe Kerello2017-09-221-0/+9
| | | | | | | | | | | | | | | This patch adds the support of reset and clock control block (rcc) found on STM32 SoCs. This driver is similar to a MFD linux driver. This driver supports currently STM32H7 only. STM32F4 and STM32F7 will be migrated to this rcc MFD driver in the future to uniformize all STM32 SoCs already upstreamed. Signed-off-by: Christophe Kerello <christophe.kerello@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Reviewed-by: Vikas Manocha <vikas.manocha@st.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* misc: Kconfig: Add SPL_I2C_EEPROM optionWenyou Yang2017-09-111-0/+8
| | | | | | | | This option is an SPL-variant of the I2C_EEPROM option to enable the driver for generic I2C-attached EEPROMs for SPL. Signed-off-by: Wenyou Yang <wenyou.yang@microchip.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Kconfig: Add EEPROM options to Kconfig when I2C_EEPROM is setAdam Ford2017-09-021-0/+45
| | | | | | | | | | | | | | | | | | Add the following options to drivers/misc/Kconfig: SYS_I2C_EEPROM_ADDR SYS_I2C_EEPROM_BUS SYS_EEPROM_SIZE SYS_EEPROM_PAGE_WRITE_BITS SYS_EEPROM_PAGE_WRITE_DELAY_MS SYS_I2C_EEPROM_ADDR_LEN SYS_I2C_EEPROM_ADDR_OVERFLOW This does not migrate any boards, but provides a foundations for those who want/need these options Signed-off-by: Adam Ford <aford173@gmail.com> [trini: Migrate uniphier] Signed-off-by: Tom Rini <trini@konsulko.com>
* drivers/misc: Add basic support for ATSHA204A Crypto moduleMarek Behún2017-07-121-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | This module can be found on the Turris Omnia board connected via the I2C interface. Among some cryptographic functions, the chip has a 512 bit One Time Programmable memory, 88 byte configuration memory and 512 byte general purpose memory. The Turris Omnia stores serial number and device MAC address in the OTP memory. This commit adds basic support for reading the EEPROM and also exposes the chips Random Number Generator. The driver is based on code by Josh Datko, Cryptotronix, jbd@cryptotronix.com and also Tomas Hlavacek, CZ.NIC, tomas.hlavacek@nic.cz Signed-off-by: Tomas Hlavacek <tomas.hlavacek@nic.cz> Signed-off-by: Marek Behun <marek.behun@nic.cz> create mode 100644 drivers/misc/atsha204a-i2c.c create mode 100644 include/atsha204a-i2c.h Signed-off-by: Stefan Roese <sr@denx.de>
* rockchip: efuse: add (misc) driver for RK3399 non-secure efuse blockPhilipp Tomsich2017-06-071-0/+13
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a simple driver for reading the efuse block of the RK3399. It should be easy enough to add drivers for other devices (e.g. the RK3328, RK3368, etc.) by passing the device details via driver_data. Unlike the kernel driver (using the nvmem subsystem), we don't expose the efuse as multiple named cells, but rather as a linear memory that can be read using misc_read(...). The primary use case (as of today) is the generation of a 'serial#' (and a 'cpuid#') environment variable for the RK3399-Q7 (Puma) system-on-module. Note that this adds a debug-only (i.e. only if DEBUG is defined) command 'rk3399_dump_efuses' that dumps the efuse block's content. N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to include a SoC-name (together with a comment in the function) to remind whoever adds support for additional SoCs that this function currently makes assumptions regarding the size of the fuse-box based on the RK3399. The hope is that the function is adjusted to reflect any changes resulting from generalising the driver for multiple SoCs and is then renamed. Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* Convert CONFIG_DS4510 to KconfigSimon Glass2017-05-221-0/+8
| | | | | | | | | This converts the following to Kconfig: CONFIG_DS4510 Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Heiko Schocher <hs@denx.de>
* misc: implement Tegra CAR core driverStephen Warren2016-09-271-0/+7
| | | | | | | | | | | | The Tegra CAR (Clock And Reset) module provides control of most clocks and reset signals within the Tegra SoC. This change implements a driver for this module. However, since the module implements multiple kinds of services (clocks, resets, perhaps more), all this driver does is bind various sub-devices, which in turn provide the real services. This driver is essentially an "MFD" (Multi-Function Device) in Linux kernel speak. Signed-off-by: Stephen Warren <swarren@nvidia.com> Signed-off-by: Tom Warren <twarren@nvidia.com>
* misc: Add simple driver for some Nuvoton NCT6102D devicesStefan Roese2016-08-161-0/+8
| | | | | | | | | | | This simple driver provides some functions to control some of the integrated devices. The watchdog is enabled per default. This driver adds a function to disable the watchdog. Also the internal legacy UART (io address 0x3f8/0x2f8) is enabled per default. Signed-off-by: Stefan Roese <sr@denx.de> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org>
* misc: add Tegra BPMP driverStephen Warren2016-08-151-0/+12
| | | | | | | | | | | | | | | The Tegra BPMP (Boot and Power Management Processor) is a separate auxiliary CPU embedded into Tegra to perform power management work, and controls related features such as clocks, resets, power domains, PMIC I2C bus, etc. This driver provides the core low-level communication path by which feature-specific drivers (such as clock) can make requests to the BPMP. This driver is similar to an MFD driver in the Linux kernel. It is unconditionally selected by CONFIG_TEGRA186 since virtually any Tegra186 build of U-Boot will need the feature. Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
* drivers/sysreset: group sysreset driversMax Filippov2016-08-121-9/+0
| | | | | | | | Create drivers/sysreset and move sysreset-uclass and all sysreset drivers there. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com> Acked-by: Simon Glass <sjg@chromium.org>
* i2c_eeprom: Add reading supportmario.six@gdsys.cc2016-07-221-0/+5
| | | | | | | | | | | | | | This patch implements the reading functionality for the generic I2C EEPROM driver, which was just a non-functional stub until now. Since the page size will be of importance for the writing support, we add suitable members to the private data structure to keep track of it. Compatibility strings for a range of at24c* chips are added. Signed-off-by: Mario Six <mario.six@gdsys.cc> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heiko Schocher <hs@denx.de>
* Rename reset to sysresetStephen Warren2016-05-261-5/+5
| | | | | | | | | | | | | | The current reset API implements a method to reset the entire system. In the near future, I'd like to introduce code that implements the device tree reset bindings; i.e. the equivalent of the Linux kernel's reset API. This controls resets to individual HW blocks or external chips with reset signals. It doesn't make sense to merge the two APIs into one since they have different semantic purposes. Resolve the naming conflict by renaming the existing reset API to sysreset instead, so the new reset API can be called just reset. Signed-off-by: Stephen Warren <swarren@nvidia.com> Acked-by: Simon Glass <sjg@chromium.org>
* cmd: qfw: rename qemu_fw_cfg.[c|h] to qfw.[c|h]Miao Yan2016-05-231-1/+1
| | | | | | | Make file names consistent with CONFIG_QFW and CONFIG_CMD_QFW Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* x86: qemu: split qfw command interface and qfw coreMiao Yan2016-05-231-0/+6
| | | | | | | | | | | | This patch splits qfw command interface and qfw core function into two files, and introduces a new Kconfig option (CONFIG_QFW) for qfw core. Now when qfw command interface is enabled, it will automatically select qfw core. This patch also makes the ACPI table generation select CONFIG_QFW. Signed-off-by: Miao Yan <yanmiaobest@gmail.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* misc: Add simple driver to enable the legacy UART on Winbond Super IO chipsStefan Roese2016-01-281-0/+8
| | | | | | | | | | | On most x86 boards, the legacy serial ports (io address 0x3f8/0x2f8) are provided by a superio chip connected to the LPC bus. We must program the superio chip so that serial ports are available for us. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Bin Meng <bmeng.cn@gmail.com> Cc: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* dm: Add a power sequencing uclassSimon Glass2016-01-211-0/+18
| | | | | | | | Some devices need special sequences to be used when starting up. Add a uclass for this. Drivers can be added to provide specific features as needed. Signed-off-by: Simon Glass <sjg@chromium.org>
* driver: misc: add MXC_OCOTP Kconfig entryPeng Fan2015-10-301-0/+7
| | | | | | | | | Add MXC_OCOTP Kconfig entry. Signed-off-by: Peng Fan <Peng.Fan@freescale.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Fabio Estevam <fabio.estevam@freescale.com>
* nios2: convert altera sysid to driver modelThomas Chou2015-10-231-0/+7
| | | | | | | | Convert altera sysid to driver model with misc uclass. Signed-off-by: Thomas Chou <thomas@wytron.com.tw> Acked-by: Chin Liang See <clsee@altera.com> Reviewed-by: Simon Glass <sjg@chromium.org>
generated by cgit (git 2.34.1) at 2026-01-05 19:03:35 +0000