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* ddr: imx8m: Fix the ddr init hang on imx8mqJacky Bai2019-10-081-4/+4
| | | | | | | | | | On, i.MX8MQ, the PLL config must be done when ddrmix isolation is released. So move the dram pll init after iso config done. For other i.MX8M SOC, either init pll before or after isolation is ok. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* driver: ddr: Refine the ddr init driver on imx8mJacky Bai2019-10-087-311/+184
| | | | | | | | | | Refine the ddr init driver to make it more reusable for different DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant code. Signed-off-by: Jacky Bai <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* imx8mq: Update the ddrc QoS setting for B1 chipBai Ping2019-10-081-1/+4
| | | | | | | | | | | | Update the ddrc Qos setting for B1 to align with B0's setting. Correct the initial clock for dram_pll. This setting will be overwrite before ddr phy training. Although there is no impact on the dram init, we still need to correct it to eliminate confusion. Signed-off-by: Bai Ping <ping.bai@nxp.com> Reviewed-by: Ye Li <ye.li@nxp.com> Tested-by: Robby Cai <robby.cai@nxp.com>
* ddr: imx8m: Fix ddr4 driver build issueYe Li2019-10-081-2/+1
| | | | | | | | Since the parameter of dram_pll_init is changed, update to use new. Also remove non-existed header file. Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: imx8m: fix ddr firmware location when enable SPL OFPeng Fan2019-10-081-1/+11
| | | | | | | | | | | With CONFIG_SPL_OF_CONTROL, the device tree will be padded to end of the u-boot-spl-nodtb.bin, however we also put the ddr firmware file to this location, so need to adapt the code with SPL OF and align to 4 bytes to ease copy firmware. Reviewed-by: Frieder Schrempf <frieder.schrempf@kontron.de> Tested-by: Frieder Schrempf <frieder.schrempf@kontron.de> Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr, fsl: add DM_I2C supportHeiko Schocher2019-08-261-43/+76
| | | | | | | add DM_I2C support for this driver. Signed-off-by: Heiko Schocher <hs@denx.de> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* boards: lx2160a: Add support of I2C driver modelChuanhua Han2019-08-221-1/+35
| | | | | | | | | | | DM_I2C_COMPAT is a compatibility layer that allows using the non-DM I2C API when DM_I2C is used. When DM_I2C_COMPAT is not enabled for compilation, a compilation error will be generated. This patch solves the problem that the i2c-related api of the lx2160a platform does not support dm. Signed-off-by: Chuanhua Han <chuanhua.han@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* env: Move env_get_f() to env.hSimon Glass2019-08-113-0/+3
| | | | | | | Move this function over to the new header file. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
* dm: ddr: socfpga: fix gen5 ddr driver to not use bssSimon Goldschmidt2019-07-212-642/+740
| | | | | | | | | | This driver uses bss from SPL board_init_f(). Change it to move all the data from bss to a common struct allocated on the stack (64 byte). In addition to saving 28 bytes of bss, the code even gets 264 bytes smaller. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* mpc83xx: Get rid of CONFIG_SYS_DDR_SDRAM_BASEMario Six2019-05-211-0/+4
| | | | | | | | CONFIG_SYS_DDR_SDRAM_BASE is set to the same value as CONFIG_SYS_SDRAM_BASE on all existing boards. Just use CONFIG_SYS_SDRAM_BASE instead. Signed-off-by: Mario Six <mario.six@gdsys.cc>
* arm: socfpga: Move Stratix 10 SDRAM driver to DMLey Foon Tan2019-05-063-77/+360
| | | | | | | | | | | | | | Convert Stratix 10 SDRAM driver to device model. Get rid of call to socfpga_per_reset() and use reset framework. SPL is changed from calling function in SDRAM driver directly to just probing UCLASS_RAM. Move sdram_s10.h from arch to driver/ddr/altera directory. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ddr: altera: Compile ALTERA SDRAM in SPL onlyLey Foon Tan2019-05-062-3/+4
| | | | | | | Compile ALTERA_SDRAM driver in SPL only. Rename ALTERA_SDRAM to SPL_ALTERA_SDRAM. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ddr: imx8m: hide i.MX8M DDR options from device driver entryPeng Fan2019-04-251-0/+4
| | | | | | | Use one menu to hide the several i.MX8M DDR options from device driver entry. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* ddr: altera: Stratix10: Add ECC memory scrubbingLey Foon Tan2019-04-171-0/+81
| | | | | | | | | | | | | Scrub memory content if ECC is enabled and it is not from warm reset boot. Enable icache and dcache before scrub memory and use "DC ZVA" instruction to clear memory to zeros. This instruction writes a cache line at a time and it can prevent false ECC error trigger if write cache line partially. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ddr: altera: Stratix10: Add multi-banks DRAM size checkLey Foon Tan2019-04-171-5/+41
| | | | | | | | | | | Stratix 10 maps dram from 0 to 128GB. There is a 2GB hole in the memory for peripherals and other IO from 2GB to 4GB. However the dram controller ignores upper address bits for smaller dram configurations. Example: a 4GB dram maps to multiple locations, every 4GB on the address. Signed-off-by: Dalon Westergreen <dalon.westergreen@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* ddr: altera: stratix10: Move SDRAM size check to SDRAM driverLey Foon Tan2019-04-171-0/+15
| | | | | | | | Move SDRAM size check to SDRAM driver. sdram_calculate_size() is called in SDRAM initialization already, avoid calling twice in size check function. Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* arm: socfpga: move gen5 SDR driver to DMSimon Goldschmidt2019-04-174-16/+173
| | | | | | | | | | | | | | | | | To clean up reset handling for socfpga gen5, port the DDR driver to DM using UCLASS_RAM and implement proper reset handling. This gets us rid of one ad-hoc call to socfpga_per_reset(). The gen5 driver is implemented in 2 distinct files. One of it (containing the calibration training) is not touched much and is kept at using hard coded addresses since the code grows even more otherwise. SPL is changed from calling hard into the DDR driver code to just probing UCLASS_RESET and UCLASS_RAM. It is happy after finding a RAM driver after that. Signed-off-by: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com>
* arm: mvebu: Add Marvell's integrated CPUsChris Packham2019-04-121-0/+4
| | | | | | | | | | | | Marvell's switch chips with integrated CPUs (collectively referred to as MSYS) share common ancestry with the Armada SoCs. Some of the IP blocks (e.g. xor) are located at different addresses and DFX server exists as a separate target on the MBUS (on Armada-38x it's just part of the core complex registers). Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* mv_ddr: ddr3: only use active chip-selects when tuning ODTChris Packham2019-03-191-1/+2
| | | | | | | | | | | Inactive chip-selects will give invalid values for read_sample so don't consider them when trying to determine the overall min/max read sample. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/18] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* mv_ddr: ddr3: fix tRAS timimg parameterChris Packham2019-03-191-4/+4
| | | | | | | | | | | | | Based on the JEDEC standard JESD79-3F. The tRAS timings should include the highest speed bins at a given frequency. This is similar to commit 683c67b ("mv_ddr: ddr3: fix tfaw timimg parameter") where the wrong comparison was used in the initial implementation. Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz> [https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/15] Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ddr: socfpga: Clean up ddr_setup()Marek Vasut2019-03-091-28/+15
| | | | | | | | | | | | | | | | Replace the current rather convoluted code using ad-hoc polling mechanism with a more straightforward code. Use wait_for_bit_le32() to poll the DDRCALSTAT register instead of local reimplementation. It makes no sense to pull for 5 seconds before giving up and trying to restart the EMIF, so instead wait 500 mSec for the calibration to complete and if this fails, restart the EMIF and try again. Perform this 32 times instead of 3 times as the original code did. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* ddr: socfpga: Clean up EMIF resetMarek Vasut2019-03-091-26/+7
| | | | | | | | | | | | | | The EMIF reset code can well use wait_for_bit_le32() instead of all that convoluted polling code. Reduce the timeout from 100 seconds to 1 second, since if the EMIF fails to reset itself in 1 second, it's unlikely longer wait would help. Make sure to clear the EMIF reset request even if the SEQ2CORE_INT_RESP_BIT isn't asserted. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* ddr: socfpga: Fix EMIF clear timeoutMarek Vasut2019-03-091-14/+11
| | | | | | | | | | | | | | | | The current EMIF clear timeout handling code was applying bitwise operations to signed data types and as it was, was extremely hard to read. Replace it with simple wait_for_bit(). Expand the error handling to make it more readable too. This patch also changes the timeout for emif_clear() from 14 hours to 1 second. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* ddr: socfpga: Fix newline in debug print on A10Marek Vasut2019-03-091-1/+1
| | | | | | | | | | The debug print is missing a newline, add it. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* ddr: socfpga: Fix IO in Arria10 DDR driverMarek Vasut2019-03-091-3/+3
| | | | | | | | | | | | The Altera Arria10 DDR driver was using constants in a few places instead of reading registers associated with those constants, fix this. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com>
* configs: fsl: move DDR specific defines to KconfigRajesh Bhagat2019-03-031-0/+12
| | | | | | | | | | | | | Moves below DDR specific defines to Kconfig: CONFIG_FSL_DDR_BIST CONFIG_FSL_DDR_FIRST_SLOT_QUAD_CAPABLE CONFIG_FSL_DDR_INTERACTIVE CONFIG_FSL_DDR_SYNC_REFRESH Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com> Reviewed-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* drivers/ddr/fsl: Update fsl_ddr_board_options as weak functionPriyanka Jain2019-02-191-3/+6
| | | | | | | | | | | | fsl_ddr_board_options is generally defined in board board's ddr.c, but some boards like lx2160ardb board does not need this function. Defining fsl_ddr_board_options as weak function to resolve compilation errors for such boards. Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> [PK: Fix checkpatch warnings] Signed-off-by: Prabhakar Kushwaha <prabhakar.kushwaha@nxp.com>
* drivers: ddr: introduce DDR driver for i.MX8MPeng Fan2019-01-0110-0/+1510
| | | | | | | Introduce DDR driver for i.MX8M. The driver will be used by SPL to initialze DDR PHY and DDR Controller. Signed-off-by: Peng Fan <peng.fan@nxp.com>
* Merge tag 'fsl-qoriq-for-v2019.01-rc2' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2018-12-101-0/+1
|\ | | | | | | | | | | | | | | Add TFA boot flow for some Layerscape platforms Add support for lx2160a SoC [trini: Add a bunch of missing MAINTAINERS entries] Signed-off-by: Tom Rini <trini@konsulko.com>
| * armv8: lx2160a: Add LX2160A SoC SupportPriyanka Jain2018-12-061-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | LX2160A Soc is based on Layerscape Chassis Generation 3.2 architecture with features: 16 ARM v8 Cortex-A72 cores in 8 cluster, CCN508, SEC, 2 64-bit DDR4 memory controller, RGMII, 8 I2C controllers, 3 serdes modules, USB 3.0, SATA, 4 PL011 SBSA UARTs, 4 TZASC instances, etc. SoC personalites: LX2120A is SoC with Twelve 64-bit ARM v8 Cortex-A72 CPUs LX2080A is SoC with Eight 64-bit ARM v8 Cortex-A72 CPUs Signed-off-by: Bao Xiaowei <xiaowei.bao@nxp.com> Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com> Signed-off-by: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com> Signed-off-by: Sriram Dash <sriram.dash@nxp.com> Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* | ARM: mvebu: restore license information in mv_ddr_plat.{c,h}Chris Packham2018-12-092-0/+9
| | | | | | | | | | | | This was unintentionally removed when syncing with upstream. Signed-off-by: Chris Packham <judge.packham@gmail.com>
* | ARM: mvebu: a38x: sync ddr training code with mv_ddr-armada-18.09.02Chris Packham2018-12-0831-1254/+1156
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-18.09 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. Specifically this syncs with commit 99d772547314 ("Bump mv_ddr to release armada-18.09.2"). The complete log of changes is best obtained from the mv-ddr-marvell.git repository but some relevant highlights are: ddr3: add missing txsdll parameter ddr3: fix tfaw timimg parameter ddr3: fix trrd timimg parameter merge ddr3 topology header file with mv_ddr_topology one mv_ddr: a38x: fix zero memory size scrubbing issue The upstream code is incorporated omitting the portions not relevant to Armada-38x and DDR3. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT -UCONFIG_A3700 -UA3900 -UA80X0 \ -UA70X0 Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Tested-by: Baruch Siach <baruch@tkos.co.il> Signed-off-by: Stefan Roese <sr@denx.de>
* socfpga: stratix10: fix sdram_calculate_sizeDalon Westergreen2018-09-151-2/+2
| | | | | | | | Incorrect type of size variable results in 0 being returned for sdram sizes greater than or equal to 4GB. Signed-off-by: Dalon Westergreen <dwesterg@gmail.com>
* drivers/ddr/fsl: fix '__hwconfig without a buffer' messagesJeremy Gebben2018-07-261-8/+6
| | | | | | | | | | Pass an empty buffer instead of NULL if the hwconfig environment variable isn't set. Signed-off-by: Jeremy Gebben <jgebben@sweptlaser.com> Cc: Stefano Babic <sbabic@denx.de> Cc: York Sun <york.sun@nxp.com> Reviewed-by: York Sun <york.sun@nxp.com>
* ddr: altera: Add ECC DRAM scrubbing support for Arria10Marek Vasut2018-07-121-0/+27
| | | | | | | | | | | | The SDRAM must first be rewritten by zeroes if ECC is used to initialize the ECC metadata. Make the CPU overwrite the DRAM with zeroes in such a case. This scrubbing implementation turns the caches on temporarily, then overwrites the whole RAM with zeroes, flushes the caches and turns them off again. This provides satisfactory performance. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
* ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10Marek Vasut2018-07-121-25/+0
| | | | | | | | | | | This function was never used in SPL and the default implementation of dram_bank_mmu_setup() does the same thing. The only difference is the part which configures OCRAM as cachable, which doesn't really work as it covers more than the OCRAM. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Chin Liang See <chin.liang.see@intel.com> Cc: Dinh Nguyen <dinguyen@kernel.org>
* ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan2018-07-122-0/+389
| | | | | | | Add DDR support for Stratix SoC Signed-off-by: Chin Liang See <chin.liang.see@intel.com> Signed-off-by: Ley Foon Tan <ley.foon.tan@intel.com>
* SPDX: Fixup SPDX tags in a few new filesTom Rini2018-05-201-2/+1
| | | | Signed-off-by: Tom Rini <trini@konsulko.com>
* configs: Add DDR Kconfig support for Arria 10Tien Fong Chee2018-05-181-1/+1
| | | | | | | This patch enables DDR Kconfig support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com> Reviewed-by: Dinh Nguyen <dinguyen@kernel.org>
* ARM: socfpga: Add DDR driver for Arria 10Tien Fong Chee2018-05-182-0/+742
| | | | | | Add DDR driver support for Arria 10. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* ARM: socfpga: Rename the gen5 sdram driver to more specific nameTien Fong Chee2018-05-182-1/+1
| | | | | | | | Current sdram driver is only applied to gen5 device, hence it is better to rename sdram driver to more specific name which is related to gen5 device. Signed-off-by: Tien Fong Chee <tien.fong.chee@intel.com>
* ARM: mvebu: a38x: Add missing SPDX license identfierChris Packham2018-05-151-1/+3
| | | | | | | | mv_ddr_build_message.c is generated in Marvell's standalone mv_ddr code. When imported into u-boot we need to add the appropriate SPDX tag and re-format it slightly. Signed-off-by: Chris Packham <judge.packham@gmail.com>
* ARM: mvebu: a38x: use non-zero size for ddr scrubbingChris Packham2018-05-143-1/+5
| | | | | | | | Make ddr3_calc_mem_cs_size() global scope and use it in ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ARM: mvebu: a38x: restore support for setting timingChris Packham2018-05-144-5/+17
| | | | | | | | | | This restores support for configuring the timing mode based on the ddr_topology. This was originally implemented in commit 90bcc3d38d2b ("driver/ddr: Add support for setting timing in hws_topology_map") but was removed as part of the upstream sync. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ARM: mvebu: a38x: sync ddr training code with upstreamChris Packham2018-05-1451-5087/+7879
| | | | | | | | | | | | | | | | | | | | | | | This syncs drivers/ddr/marvell/a38x/ with the mv_ddr-armada-17.10 branch of https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git. The upstream code is incorporated omitting the ddr4 and apn806 and folding the nested a38x directory up one level. After that a semi-automated step is used to drop unused features with unifdef find drivers/ddr/marvell/a38x/ -name '*.[ch]' | \ xargs unifdef -m -UMV_DDR -UMV_DDR_ATF -UCONFIG_DDR4 \ -UCONFIG_APN806 -UCONFIG_MC_STATIC \ -UCONFIG_MC_STATIC_PRINT -UCONFIG_PHY_STATIC \ -UCONFIG_64BIT INTER_REGS_BASE is updated to be defined as SOC_REGS_PHY_BASE. Some now empty files are removed and the ternary license is replaced with a SPDX GPL-2.0+ identifier. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ARM: mvebu: a38x: remove some unused codeChris Packham2018-05-147-794/+0
| | | | | | | | | No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to remove unused sections in the rest of the ddr/marvell/a38x code. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ARM: mvebu: a38x: move sys_env_device_rev_getChris Packham2018-05-141-24/+0
| | | | | | | | | | Move sys_env_device_rev_get() from the ddr training code to sys_env_lib.c (which currently resides with the serdes code). This brings sys_env_device_rev_get() into line with sys_env_device_id_get() and sys_env_model_get(). Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ARM: mvebu: a38x: move definition of PEX_CFG_DIRECT_ACCESSChris Packham2018-05-141-2/+0
| | | | | | | | | | | PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite only being used in the serdes code. Move this definition to ctrl_pex.h where all the other PEX defines are. Also remove the duplicate definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in ctrl_pex.h. Signed-off-by: Chris Packham <judge.packham@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-0790-185/+90
| | | | | | | | | | | | | | | | | | | | When U-Boot started using SPDX tags we were among the early adopters and there weren't a lot of other examples to borrow from. So we picked the area of the file that usually had a full license text and replaced it with an appropriate SPDX-License-Identifier: entry. Since then, the Linux Kernel has adopted SPDX tags and they place it as the very first line in a file (except where shebangs are used, then it's second line) and with slightly different comment styles than us. In part due to community overlap, in part due to better tag visibility and in part for other minor reasons, switch over to that style. This commit changes all instances where we have a single declared license in the tag as both the before and after are identical in tag contents. There's also a few places where I found we did not have a tag and have introduced one. Signed-off-by: Tom Rini <trini@konsulko.com>
* Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini2018-04-272-4/+0
| | | | | | | | We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
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