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* ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See2016-10-271-0/+3
* Various, accumulated typos collected from around the tree.Robert P. J. Day2016-10-061-1/+1
* Merge git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-09-264-40/+213
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| * driver: ddr: fsl_mmdc: Pass board parameters through data structureYork Sun2016-09-261-19/+19
| * ddr: fsl: fix a compile issueShaohui Xie2016-09-141-1/+6
| * driver/ddr/fsl: Add general MMDC driver and reuse common MMDC driver for ls1012aShengzhou Liu2016-09-142-0/+157
| * driver/ddr/fsl: Revise workaround A008511 for A009803York Sun2016-09-141-36/+47
| * driver/ddr/fsl: Add more debug registersYork Sun2016-09-142-3/+3
* | drivers: squash lines for immediate returnMasahiro Yamada2016-09-233-25/+5
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* driver/ddr/fsl: Fix timing_cfg_2York Sun2016-08-021-1/+1
* Various, unrelated tree-wide typo fixes.Robert P. J. Day2016-07-161-1/+1
* driver/ddr/fsl: Check condition for erratum A-009803Shengzhou Liu2016-06-031-19/+23
* drivers/ddr/fsl: Disabling data init if ECC is not enabledYork Sun2016-06-031-1/+2
* drivers/ddr/fsl: Fix timing_cfg_2 registerYork Sun2016-06-031-1/+1
* drivers/ddr/fsl: Update clk_adjust of sdram_clk_cntlShengzhou Liu2016-06-031-2/+9
* Merge branch 'master' of git://git.denx.de/u-boot-fsl-qoriqTom Rini2016-05-241-4/+23
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| * driver/ddr/fsl: Add workaround for erratum A-010165Shengzhou Liu2016-05-181-1/+9
| * driver/ddr/fsl: Add workaround for erratum A-009801Shengzhou Liu2016-05-171-0/+7
| * drivers/ddr/fsl: update workaround for erratum A-008511Shengzhou Liu2016-05-171-3/+7
* | arm: mvebu: a38x: Weed out floating point useMarek Vasut2016-05-201-19/+10
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* Fix spelling of "occurred".Vagrant Cascadian2016-05-022-2/+2
* ddr: altera: Repair DQ window centering codeMarek Vasut2016-04-201-8/+7
* ddr: altera: Staticize global variablesMarek Vasut2016-04-201-4/+4
* ddr: altera: Make DLEVEL behavior inclusiveMarek Vasut2016-04-201-66/+66
* ddr: altera: Zero DM IN delay in scc_mgr_zero_group()Marek Vasut2016-04-201-3/+13
* ddr: altera: Remove unnecessary ODT mode configMarek Vasut2016-04-201-1/+0
* ddr: altera: Remove unnecessary update of the SCCMarek Vasut2016-04-201-1/+0
* ddr: altera: Fix DRAM end value in protection ruleMarek Vasut2016-04-201-1/+1
* ddr: altera: Fix scc_mgr_set() argument orderMarek Vasut2016-04-201-1/+1
* ddr: altera: Tweak DQS tracking enable handlingMarek Vasut2016-04-201-2/+5
* ddr: altera: Replace ad-hoc constant with macroMarek Vasut2016-04-201-2/+2
* Fix typo choosen in comments and printf logsAlexander Merkle2016-03-271-2/+2
* arm: mvebu: Fix ddr3_init() cpu configDirk Eibach2016-03-241-2/+0
* driver/ddr/fsl: Add workaround for erratum A-009803Shengzhou Liu2016-03-211-5/+39
* driver/ddr/fsl: Add address parity support for DDR4 UDIMM/discreteShengzhou Liu2016-03-212-7/+63
* Use correct spelling of "U-Boot"Bin Meng2016-02-061-1/+1
* drivers: ddr: Add DDR2 SDRAM controller driver for Microchip PIC32.Purna Chandra Mandal2016-02-014-0/+497
* drivers/ddr/fsl: fsl_ddr_sdram_size remove unused controllersEd Swarthout2016-01-251-0/+1
* driver/ddr/fsl: Add workaround for A009663Shengzhou Liu2016-01-251-0/+10
* fsl/ddr: Add workaround for ERRATUM_A009942Shengzhou Liu2016-01-251-0/+18
* Add more SPDX-License-Identifier tagsTom Rini2016-01-1910-30/+10
* ddr: altera: Init the rule ID in debug codeMarek Vasut2016-01-161-0/+1
* mvebu: axp: Rename MV_DDR_32BIT to CONFIG_DDR_32BITPhil Sutter2016-01-142-11/+11
* axp: Fix debugging support in DDR3 write levelingPhil Sutter2016-01-141-2/+2
* arm: mvebu: Make ECC support configurable on Armada XPStefan Roese2016-01-142-0/+8
* arm: mvebu: ddr: Fix compilation warningStefan Roese2016-01-142-17/+0
* move erratum a008336 and a008514 to soc specific fileYao Yuan2015-12-151-34/+0
* fsl/ddr: updated ddr errata-A008378 for arm and power SoCsShengzhou Liu2015-12-131-3/+6
* driver/ddr/fsl: Update timing config for heavy loadYork Sun2015-12-131-2/+24
* driver/ddr/fsl: Update workaround for A008511 for vref rangeYork Sun2015-12-131-7/+15
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