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path: root/drivers/ddr/altera
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* treewide: convert bd_t to struct bd_info by coccinelleMasahiro Yamada2020-07-174-6/+6
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-182-0/+2
* common: Drop linux/delay.h from common headerSimon Glass2020-05-181-0/+1
* common: Drop log.h from common headerSimon Glass2020-05-186-0/+6
* common: Drop init.h from common headerSimon Glass2020-05-182-0/+2
* common: Drop net.h from common headerSimon Glass2020-05-182-0/+2
* Merge tag 'dm-pull-6feb20' of https://gitlab.denx.de/u-boot/custodians/u-boot-dmTom Rini2020-02-112-0/+2
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| * dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-052-0/+2
* | ddr: altera: Add DDR2 support to Gen5 driverMarek Vasut2020-02-053-38/+163
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* common: Move hang() to the same header as panic()Simon Glass2020-01-173-0/+3
* common: Move RAM-sizing functions to init.hSimon Glass2020-01-172-0/+2
* ddr: socfpga: Enable ARM64 Non-Secure SDRAM ECC AccessThor Thayer2020-01-072-6/+6
* arm: socfpga: stratix10: Enable SMMU accessThor Thayer2020-01-071-0/+14
* ddr: altera: agilex: Add SDRAM driver for AgilexLey Foon Tan2020-01-075-3/+174
* ddr: altera: Restructure Stratix 10 SDRAM driverLey Foon Tan2020-01-075-443/+493
* arm: socfpga: Move Stratix10 and Agilex system manager common codeLey Foon Tan2020-01-071-1/+1
* arm: socfpga: Move firewall code to firewall fileLey Foon Tan2020-01-071-1/+1
* arm: socfpga: Convert system manager from struct to definesLey Foon Tan2020-01-072-10/+8
* common: Move some cache and MMU functions out of common.hSimon Glass2019-12-022-0/+2
* ddr: socfpga: gen5: constify altera_gen5_sdram_opsSimon Goldschmidt2019-11-201-1/+1
* dm: ddr: socfpga: fix gen5 ddr driver to not use bssSimon Goldschmidt2019-07-212-642/+740
* arm: socfpga: Move Stratix 10 SDRAM driver to DMLey Foon Tan2019-05-063-77/+360
* ddr: altera: Compile ALTERA SDRAM in SPL onlyLey Foon Tan2019-05-062-3/+4
* ddr: altera: Stratix10: Add ECC memory scrubbingLey Foon Tan2019-04-171-0/+81
* ddr: altera: Stratix10: Add multi-banks DRAM size checkLey Foon Tan2019-04-171-5/+41
* ddr: altera: stratix10: Move SDRAM size check to SDRAM driverLey Foon Tan2019-04-171-0/+15
* arm: socfpga: move gen5 SDR driver to DMSimon Goldschmidt2019-04-174-16/+173
* ddr: socfpga: Clean up ddr_setup()Marek Vasut2019-03-091-28/+15
* ddr: socfpga: Clean up EMIF resetMarek Vasut2019-03-091-26/+7
* ddr: socfpga: Fix EMIF clear timeoutMarek Vasut2019-03-091-14/+11
* ddr: socfpga: Fix newline in debug print on A10Marek Vasut2019-03-091-1/+1
* ddr: socfpga: Fix IO in Arria10 DDR driverMarek Vasut2019-03-091-3/+3
* socfpga: stratix10: fix sdram_calculate_sizeDalon Westergreen2018-09-151-2/+2
* ddr: altera: Add ECC DRAM scrubbing support for Arria10Marek Vasut2018-07-121-0/+27
* ddr: altera: Drop custom dram_bank_mmu_setup() on Arria10Marek Vasut2018-07-121-25/+0
* ddr: altera: stratix10: Add DDR support for Stratix10 SoCLey Foon Tan2018-07-122-0/+389
* SPDX: Fixup SPDX tags in a few new filesTom Rini2018-05-201-2/+1
* configs: Add DDR Kconfig support for Arria 10Tien Fong Chee2018-05-181-1/+1
* ARM: socfpga: Add DDR driver for Arria 10Tien Fong Chee2018-05-182-0/+742
* ARM: socfpga: Rename the gen5 sdram driver to more specific nameTien Fong Chee2018-05-182-1/+1
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-074-9/+4
* Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini2018-04-271-2/+0
* ddr: altera: silence PHY calibration unless in debug modeGoldschmidt Simon2018-01-251-4/+4
* arm: socfpga: Convert Altera DDR SDRAM driver to use KconfigLey Foon Tan2017-04-142-1/+8
* ddr: altera: Configuring SDRAM extra cycles timing parametersChin Liang See2016-10-271-0/+3
* ddr: altera: Repair DQ window centering codeMarek Vasut2016-04-201-8/+7
* ddr: altera: Staticize global variablesMarek Vasut2016-04-201-4/+4
* ddr: altera: Make DLEVEL behavior inclusiveMarek Vasut2016-04-201-66/+66
* ddr: altera: Zero DM IN delay in scc_mgr_zero_group()Marek Vasut2016-04-201-3/+13
* ddr: altera: Remove unnecessary ODT mode configMarek Vasut2016-04-201-1/+0