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path: root/drivers/clk/sifive
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* clk: sifive: fu540-prci: Release ethernet clock resetPragnesh Patel2020-06-041-0/+20
* clk: sifive: fu540-prci: Add ddr clock initializationPragnesh Patel2020-06-041-6/+45
* clk: sifive: fu540-prci: Add clock enable and disable opsPragnesh Patel2020-06-041-12/+96
* common: Drop linux/delay.h from common headerSimon Glass2020-05-181-0/+1
* dm: core: Require users of devres to include the headerSimon Glass2020-02-051-0/+1
* clk: sifive: Drop GEMGXL clock driverAnup Patel2019-07-193-69/+0
* clk: sifive: Sync-up main driver with upstream LinuxAnup Patel2019-07-191-36/+60
* clk: sifive: Sync-up DT bindings header with upstream LinuxAnup Patel2019-07-191-1/+1
* clk: sifive: Sync-up WRPLL library with upstream LinuxAnup Patel2019-07-191-13/+13
* clk: sifive: Factor-out PLL library as separate moduleAnup Patel2019-07-195-498/+1
* clk: sifive: Add clock driver for GEMGXL MGMTBin Meng2019-06-013-0/+69
* clk: sifive: fu540-prci: Change include orderJagan Teki2019-05-091-1/+1
* clk: Add SiFive FU540 PRCI clock driverAnup Patel2019-02-275-0/+1119
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