summaryrefslogtreecommitdiffstats
path: root/drivers/clk/rockchip
Commit message (Expand)AuthorAgeFilesLines
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-025-0/+5
* dm: Use access methods for dev/uclass private dataSimon Glass2021-01-0511-11/+20
* dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-1311-26/+26
* dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2020-12-134-5/+5
* dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-134-5/+5
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-1311-18/+18
* rockchip: rk3399: Init clocks in U-Boot proper if SPL was not runAlper Nebi Yasak2020-11-131-6/+16
* Merge tag 'u-boot-rockchip-20201031' of https://gitlab.denx.de/u-boot/custodi...Tom Rini2020-10-301-0/+20
|\
| * clk: rockchip: rk3399: implement getting wdt/alive clocksJack Mitchell2020-10-301-0/+20
* | treewide: Fix wrong CONFIG_IS_ENABLED() handlingAlper Nebi Yasak2020-10-141-1/+1
|/
* drivers: clk: rockchip: clk_rk3328: Add SPI supportJohannes Krottmayer2020-07-221-0/+31
* rockchip: clk: rk3188: change APLL to safe 600MHzAlexander Kochetkov2020-06-271-1/+2
* clk: rk3399: Enable/Disable TCPHY clocksJagan Teki2020-05-291-0/+24
* clk: rk3399: Set empty for TCPHY assigned-clocksJagan Teki2020-05-291-0/+2
* clk: rk3399: Enable/Disable the USB2PHY clkJagan Teki2020-05-291-0/+12
* clk: rk3399: Fix eMMC get_clk reg offsetJagan Teki2020-05-291-1/+1
* clk: rk3399: Enable/Disable the PCIEPHY clkJagan Teki2020-05-221-0/+6
* clk: rk3399: Add enable/disable clksJagan Teki2020-05-221-0/+148
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-186-0/+6
* common: Drop linux/delay.h from common headerSimon Glass2020-05-1811-0/+11
* common: Drop linux/stringify.h from common headerSimon Glass2020-05-186-0/+6
* common: Drop log.h from common headerSimon Glass2020-05-1812-0/+12
* clk: rk3399: Set empty for HCLK_SD assigned-clocksJagan Teki2020-05-011-0/+1
* clk: rk3399: Set empty for vopl assigned-clocksJagan Teki2020-04-021-0/+7
* dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-0511-0/+11
* dm: core: Require users of devres to include the headerSimon Glass2020-02-052-0/+2
* arm: rockchip: Add common cru.hJagan Teki2020-01-302-39/+39
* rockchip: clk: Add clk driver for rk3308Finley Xiao2019-11-172-0/+1073
* rockchip: clk: pll: add common pll setting funcsElaine Zhang2019-11-172-0/+361
* rockchip: clk: fix wrong CONFIG_IS_ENABLED handlingHeiko Stuebner2019-11-178-8/+8
* rockchip: clk: rv1108: remove duplicate reset initHeiko Stuebner2019-11-171-14/+2
* rockchip: clk: add px30 clock driverKever Yang2019-11-172-0/+1631
* clk: rockchip: rk3328: Configure CPU clockSimon South2019-11-101-0/+2
* rockchip: clk: rk3399: remove clk_enable()Kever Yang2019-09-111-37/+0
* rockchip: clk: rk3368: remove clk_enable()Kever Yang2019-09-111-19/+0
* rockchip: clk: rk3328: remove clk_enable()Kever Yang2019-09-111-12/+0
* rockchip: clk: rk3288: remove clk_enable()Kever Yang2019-09-111-23/+0
* rockchip: clk: rk3328: add clk_enable ops for HCLK_HOST0Kever Yang2019-08-231-0/+12
* rockchip: rk3188: init CPU freq in clock driverKever Yang2019-07-291-0/+3
* clk: rockchip: rk3399: Set 400MHz ddr clockJagan Teki2019-07-211-0/+4
* clk: rockchip: rk3399: Set 50MHz ddr clockJagan Teki2019-07-211-0/+4
* clk: rockchip: rk3399: Fix check patch warnings and checksJagan Teki2019-07-191-37/+31
* rockchip: clk: rk3399: handle clk_enable requests for USB3Mark Kettenis2019-07-191-0/+12
* rockchip: clk: rk3399: allow requests for all UART clocksChristoph Muellner2019-05-301-0/+2
* rockchip: clk: rk322x: fix assert clock valueKever Yang2019-05-081-2/+2
* rockchip: rk322x: add CLK_EMMC_SAMPLE clock supportKever Yang2019-05-081-0/+2
* rockchip: use 'arch-rockchip' as header file pathKever Yang2019-05-019-30/+30
* rockchip: clk: Add mention of four new clocksSimon Glass2019-02-011-0/+12
* rockchip: rk3288: Add i2s pinctrl and clock supportSimon Glass2019-02-011-0/+48
* rockchip: rk3399: Initialize CPU B clock.Christoph Muellner2018-11-301-9/+70
generated by cgit (git 2.34.1) at 2026-01-08 07:46:22 +0000