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path: root/drivers/clk/renesas/renesas-cpg-mssr.h
Commit message (Expand)AuthorAgeFilesLines
* clk: renesas: Add register pointers into struct cpg_mssr_infoHai Pham2021-05-211-0/+52
* clk: renesas: Introduce enum clk_reg_layoutHai Pham2021-05-211-0/+6
* clk: renesas: Pass struct cpg_mssr_info to renesas_clk_endisable()Hai Pham2021-05-211-1/+2
* clk: renesas: Make reset controller modemr register offset configurableMarek Vasut2021-05-211-0/+1
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-181-0/+1
* clk: renesas: Synchronize Gen3 tables with Linux 5.0Marek Vasut2019-04-091-0/+3
* SPDX: Convert all of our single license tags to Linux Kernel styleTom Rini2018-05-071-2/+1
* clk: renesas: Add Gen2 clock coreMarek Vasut2018-01-241-0/+3
* clk: renesas: Add DIV6P1 clock typeMarek Vasut2018-01-241-0/+6
* clk: renesas: Split out code shared between Gen2 and Gen3Marek Vasut2018-01-241-0/+10
* clk: renesas: Split SMSTPCR and RMSTPCR tablesMarek Vasut2018-01-241-2/+4
* clk: renesas: Pull Gen3 specific bits into separate headerMarek Vasut2018-01-241-41/+0
* clk: renesas: Make PLL configurations per-SoCMarek Vasut2018-01-241-0/+1
* clk: renesas: Make clk_ids per-driverMarek Vasut2018-01-241-37/+3
* clk: renesas: Split RCar Gen3 driverMarek Vasut2018-01-241-0/+170
generated by cgit (git 2.34.1) at 2024-06-10 19:28:07 +0000