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path: root/drivers/clk/kendryte
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* treewide: Convert macro and uses of __section(foo) to __section("foo")Marek BehĂșn2021-05-241-2/+2
| | | | | | | | | | | | | | | | | This commit does the same thing as Linux commit 33def8498fdd. Use a more generic form for __section that requires quotes to avoid complications with clang and gcc differences. Remove the quote operator # from compiler_attributes.h __section macro. Convert all unquoted __section(foo) uses to quoted __section("foo"). Also convert __attribute__((section("foo"))) uses to __section("foo") even if the __attribute__ has multiple list entry forms. Signed-off-by: Marek BehĂșn <marek.behun@nic.cz> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org>
* clk: Add support for the k210 clock driver pre-relocationSean Anderson2021-05-141-4/+10
| | | | | | | | Variables which had previously been stored in .bss are moved to .data. In addition, probed needs to be reset when the clock driver is re-bound post-relocation. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* clk: k210: Move the clint clock to under aclkSean Anderson2021-05-141-1/+1
| | | | | | | No other (real) clocks have the cpu clock as their parent; instead they are children of aclk. Move the clint clock under aclk to match them. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* clk: k210: Remove k210_register_pllSean Anderson2021-05-142-28/+3
| | | | | | | This simplifies the PLL creation process, since we don't have to pass all the parameters individually. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* clk: k210: Fix PLL enable always getting takenSean Anderson2021-05-141-1/+2
| | | | | | | | | This conditional always evaluated as false, regardless of the value of reg. Fix it so that it properly tests the bits in the PLL register. Also test PLL_EN, now that we set it. Reported-by: Damien Le Moal <Damien.LeMoal@wdc.com> Signed-off-by: Sean Anderson <seanga2@gmail.com>
* clk: k210: Fix PLLs not being enabledSean Anderson2021-05-141-0/+2
| | | | | | | | | | After starting or setting the rate of a PLL, the enable bit must be set. This fixes a bug where the AI ram would not be accessible, because it requires PLL1 to be running. Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Damien Le Moal <damien.lemoal@wdc.com>
* clk: Update drivers to use -EINVALSimon Glass2021-04-062-2/+2
| | | | | | | | | | | At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* clk: kendryte: no need to check argument of free()Heinrich Schuchardt2020-10-261-2/+1
| | | | | | | free() checks if its argument is NULL. No need to check it twice. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* riscv: clk: Add CLINT clock to kendryte clock driverSean Anderson2020-09-301-0/+4
| | | | | | | | Another "virtual" clock (in the sense that it isn't configurable). This could possibly be done as a clock in the device tree, but I think this is a bit cleaner. Signed-off-by: Sean Anderson <seanga2@gmail.com>
* clk: Drop dm.h header file in clk-provider.hSimon Glass2020-08-032-6/+11
| | | | | | | | | | | This header file should not be included in other header files. Remove it and use a forward declaration and un-inlining of dev_get_clk_ptr() instead. Fix up the kendryte header files to avoid build errors. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Sean Anderson <seanga2@gmail.com>
* clk: Add K210 clock supportSean Anderson2020-07-013-2/+665
| | | | | | | | | | Due to the large number of clocks, I decided to use the CCF. The overall structure is modeled after the imx code. Clocks parameters are stored in several arrays, and are then instantiated at run-time. There are some translation macros (FOOIFY()) which allow for more dense packing. Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
* clk: Add a bypass clock for K210Sean Anderson2020-07-012-1/+271
| | | | | | | | | | | This is a small driver to do a software bypass of a clock if hardware bypass is not working. I have tried to write this in a generic fashion, so that it could be potentially broken out of the kendryte code at some future date. For the K210, it is used to have aclk bypass pll0 and use in0 instead so that the CPU keeps on working. Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>
* clk: Add K210 pll supportSean Anderson2020-07-013-0/+614
This pll code is primarily based on the code from the kendryte standalone sdk in lib/drivers/sysctl.c. k210_pll_calc_config is roughly analogous to the algorithm used to set the pll frequency, but it has been completely rewritten to be fixed-point based. Signed-off-by: Sean Anderson <seanga2@gmail.com> CC: Lukasz Majewski <lukma@denx.de>