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path: root/drivers/clk/imx/clk-pllv3.c
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* clk: Update drivers to use -EINVALSimon Glass2021-04-061-1/+1
| | | | | | | | | | | At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* clk: imx: Add support for pllv3 enet clockLukasz Majewski2020-08-241-0/+25
| | | | | | | | | | This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM. It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver. Signed-off-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: add enable_bitGiulio Benetti2020-04-181-0/+9
| | | | | | | | | pllv3 PLLs have powerdown/up bits but enable bits too. Specifically "enable bit" enable the pll output, so when dis/enabling pll by setting/clearing power_bit we must also set/clear enable_bit. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* dm: core: Require users of devres to include the headerSimon Glass2020-02-051-0/+2
| | | | | | | | | | At present devres.h is included in all files that include dm.h but few make use of it. Also this pulls in linux/compat which adds several more headers. Drop the automatic inclusion and require files to include devres themselves. This provides a good indication of which files use devres. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Anatolij Gustschin <agust@denx.de>
* clk: imx: pllv3: fix potential 'divide by zero' in av_set_rate()Giulio Benetti2020-01-261-2/+8
| | | | | | | Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_av_set_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: pllv3: fix potential 'divide by zero' in av_get_rate()Giulio Benetti2020-01-261-0/+3
| | | | | | | | Guard 'mfd==0' to prevent 'divide by zero' issue in clk_pplv3_av_get_rate(). If it is 0, let's return with EIO since mfd should never be 0 at all. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: pllv3: fix potential 'divide by zero' in sys_get_rate()Giulio Benetti2020-01-261-2/+8
| | | | | | | Guard 'parent_rate==0' to prevent 'divide by zero' issue in clk_pplv3_sys_get_rate(). If it is 0, let's return with -EINVAL. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: pllv3: add support for PLLV3_AV typeGiulio Benetti2020-01-141-0/+76
| | | | | | Add support for PLLV3 AV type. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: pllv3: add PLLV3_SYS supportGiulio Benetti2020-01-141-0/+53
| | | | | | | | | Add PLLV3_SYS support by adding set/get_rate() for PLLV3_SYS but keeping generic enable()/disable(). Add a different driver because ops are different respect to GENERIC/USB. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: add set_rate() supportGiulio Benetti2020-01-141-0/+27
| | | | | | | Add generic set_rate() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: add disable() supportGiulio Benetti2020-01-141-0/+16
| | | | | | | Add disable() support. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: add enable() supportGiulio Benetti2020-01-141-0/+24
| | | | | | | | | Before set_rate() pllv3 needs enable() to power the pll up. Add enable() taking into account different power_bit and different powerup_set, because some pll needs its power_bit to be set or reset to be powered on. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com>
* clk: imx: pllv3: set div_mask differently if PLLV3 is GENERIC or USBGiulio Benetti2020-01-141-0/+2
| | | | | | | div_mask is different for GENERIC and USB pll, so set it according. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: imx: pllv3: register PLLV3 GENERIC and USB as 2 different clocksGiulio Benetti2020-01-141-5/+15
| | | | | | | | | Better to register the 2 clock as 2 different drivers because they work slightly differently depending on power_bit and powerup_set bits coming on next patches. Signed-off-by: Giulio Benetti <giulio.benetti@benettiengineering.com> Reviewed-by: Lukasz Majewski <lukma@denx.de>
* clk: Port Linux common clock framework [CCF] for imx6q to U-boot (tag: v5.1.12)Lukasz Majewski2019-07-191-0/+82
This patch brings the files from Linux kernel (linux-stable/linux-5.1.y SHA1: 5752b50477da)to provide clocks support as it is used on the Linux kernel with Common Clock Framework [CCF] setup. The directory structure has been preserved. The ported code only supports reading information from PLL, MUX, Divider, etc and enabling/disabling the clocks USDHCx/ECSPIx depending on used bus. Moreover, it is agnostic to the alias numbering as the information about the clock is read from the device tree. One needs to pay attention to the comments indicating necessary for U-Boot's driver model changes. If needed, the code can be extended to support the "set" part of the clock management. Signed-off-by: Lukasz Majewski <lukma@denx.de>
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