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path: root/drivers/clk/clk-hsdk-cgu.c
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* clk: Update drivers to use -EINVALSimon Glass2021-04-061-2/+2
| | | | | | | | | | | At present some drivers use -ENOSUPP to indicate that an unknown or unsupported clock is used. Most use -EINVAL, indicating an invalid value, so convert everything to that. Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de>
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-131-1/+1
| | | | | | | | | | | | This construct is quite long-winded. In earlier days it made some sense since auto-allocation was a strange concept. But with driver model now used pretty universally, we can shorten this to 'auto'. This reduces verbosity and makes it easier to read. Coincidentally it also ensures that every declaration is on one line, thus making dtoc's job easier. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/delay.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop linux/bug.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this uncommon header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* common: Drop log.h from common headerSimon Glass2020-05-181-0/+1
| | | | | | Move this header out of the common header. Signed-off-by: Simon Glass <sjg@chromium.org>
* CLK: ARC: HSDK: add separate clock map for HSDK-4xDEugeniy Paltsev2020-05-131-8/+60
| | | | | | | | | | | HSDK and HSDK-4xD clock trees are slightly different. commit 1dfb2ec0d7fb ("ARC: HSDK: CGU: add support for timer clock") introduce regression for HSDK board cause crash when setting tunnel clock. Fix that. Fixes: 1dfb2ec0d7fb ("ARC: HSDK: CGU: add support for timer clock") Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* CLK: ARC: HSDK: define clock map with DT binding constantsEugeniy Paltsev2020-05-131-27/+29
| | | | | | | | Define clock map with DT binding constants so clock map can be discontinuous. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* CLK: ARC: HSDK: make set_clock optionalEugeniy Paltsev2020-05-131-1/+4
| | | | | | | | We don't want to allow change some clocks, i.e. DDR clock. So allow to have set_clock to be unset in clock map. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* CLK: ARC: HSDK: prepare for multiple clock maps supportEugeniy Paltsev2020-05-131-7/+20
| | | | | | | | The clock trees of HSDK and HSDK-4xD vary so we need to prepare CGU driver for multiple clock maps support. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* CLK: ARC: HSDK: driver cleanupEugeniy Paltsev2020-05-131-36/+39
| | | | | | | Minor code cleanup to improve readability. No functional change intended. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* CLK: ARC: HSDK: use appropriate config data typesEugeniy Paltsev2020-05-131-20/+21
| | | | | | | | * constify clocks config data where is possible * use more appropriate data types for clocks config Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* CLK: ARC: HSDK: drop unused offsetEugeniy Paltsev2020-05-131-29/+28
| | | | | | | | Drop creg_div_oft offset as it doesn't vary (due to it is used for CPU PLL only). Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* CLK: ARC: HSDK: avoid code duplicationEugeniy Paltsev2020-05-131-72/+40
| | | | | | | | | hsdk_axi_clk_cfg and hsdk_tun_clk_cfg clock divider structures and functions for their processing are almost the same so merge them to avoid code duplication. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* ARC: HSDK: CGU: add support for timer clockEugeniy Paltsev2020-04-271-3/+6
| | | | | | | | Add support for additional timer clock which belongs to tunnel domain. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* ARC: HSDK: CGU: fix tunnel clock calculationEugeniy Paltsev2020-04-161-1/+2
| | | | | | | | We set wrong tunnel PLL frequency when we request 125MHz tunnel clock. Fix that. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* CLK: HSDK: fix HDMI clock calculationEugeniy Paltsev2020-02-121-10/+21
| | | | | | | | | HDMI PLL has its own xtal with 27 MHz output but we treat it the same way as other PLLs with 33.33 MHz input. Fix that. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* CLK: HSDK: Check for PLL bypass firstlyEugeniy Paltsev2020-02-121-4/+4
| | | | | | | Pll bypass has priority over enable/disable. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* Remove unnecessary instances of DECLARE_GLOBAL_DATA_PTRTom Rini2018-04-271-2/+0
| | | | | | | | We have a large number of places where while we historically referenced gd in the code we no longer do, as well as cases where the code added that line "just in case" during development and never dropped it. Signed-off-by: Tom Rini <trini@konsulko.com>
* ARC: HSDK: CGU: Add 'Hz' when printing clock frequencyEugeniy Paltsev2018-01-191-3/+3
| | | | | | | Add 'Hz' when printing clock frequency in error messages. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* ARC: HSDK: CGU: Use plat data instead of priv dataEugeniy Paltsev2018-01-191-1/+1
| | | | | | | | Correctly allocate hsdk_cgu_clk private data structure using priv_auto_alloc_size instead of platdata_auto_alloc_size. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* ARC: HSDK: CGU: Update AXI, TUN, ARC clock optionsEugeniy Paltsev2018-01-191-6/+163
| | | | | | | | | | | Update default AXI, TUN, ARC clock set options: instead of changing only IDIV divider settings adjust also domain PLL settings. Add support of TUN_ROM and TUN_PWM clocks (subclocks of TUNN_PLL) Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
* ARC: clk: introduce HSDK CGU clock driverEugeniy Paltsev2017-12-111-0/+564
Synopsys HSDK clock controller generates and supplies clocks to various controllers and peripherals within the SoC. Each clock has assigned identifier and client device tree nodes can use this identifier to specify the clock which they consume. All available clocks are defined as preprocessor macros in the dt-bindings/clock/snps,hsdk-cgu.h header and can be used in device tree sources. Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com> Signed-off-by: Alexey Brodkin <abrodkin@synopsys.com>
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