summaryrefslogtreecommitdiffstats
path: root/drivers/clk/altera
Commit message (Expand)AuthorAgeFilesLines
* common: Drop asm/global_data.h from common headerSimon Glass2021-02-022-0/+2
* dm: treewide: Rename ..._platdata variables to just ..._platSimon Glass2020-12-132-34/+34
* dm: treewide: Rename ofdata_to_platdata() to of_to_plat()Simon Glass2020-12-132-4/+4
* dm: treewide: Rename dev_get_platdata() to dev_get_plat()Simon Glass2020-12-132-10/+10
* dm: treewide: Rename 'platdata' variables to just 'plat'Simon Glass2020-12-132-2/+2
* dm: treewide: Rename auto_alloc_size members to be shorterSimon Glass2020-12-132-2/+2
* clk: agilex: Additional membus writes for HPS PLLChee Hong Ang2020-10-091-16/+78
* clk: agilex: Handle clock configuration differently in SPL and U-Boot properChee Hong Ang2020-10-091-0/+10
* clk: agilex: Add clock enable supportLey Foon Tan2020-10-091-0/+6
* clk: agilex: Add NAND clock supportLey Foon Tan2020-10-091-0/+3
* treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-252-2/+2
* Revert "Merge tag 'dm-pull-20jul20' of git://git.denx.de/u-boot-dm"Tom Rini2020-07-242-2/+2
* treewide: convert devfdt_get_addr() to dev_read_addr()Masahiro Yamada2020-07-202-2/+2
* common: Drop linux/bitops.h from common headerSimon Glass2020-05-183-0/+6
* common: Drop log.h from common headerSimon Glass2020-05-181-0/+1
* dm: core: remove the duplicated function dm_ofnode_pre_relocPatrick Delaunay2020-04-161-1/+1
* clk: socfpga: Read the clock parent's register base in probe functionChee Hong Ang2020-04-051-22/+18
* dm: core: Create a new header file for 'compat' featuresSimon Glass2020-02-051-0/+2
* dm: core: Require users of devres to include the headerSimon Glass2020-02-051-0/+1
* clk: agilex: Add clock driver for AgilexLey Foon Tan2020-01-073-0/+817
* clk: socfpga: replace dm_fdt_pre_reloc by dm_ofnode_pre_relocPatrick Delaunay2019-04-111-1/+2
* clk: Remove DM_FLAG_PRE_RELOC flag in various driversBin Meng2018-11-141-1/+0
* drivers: cosmetic: Convert SPDX license tags to Linux Kernel stylePatrick Delaunay2018-10-281-2/+1
* clk: socfpga: Add initial Arria10 clock driverMarek Vasut2018-08-132-0/+370
generated by cgit (git 2.34.1) at 2024-11-15 20:17:57 +0000