summaryrefslogtreecommitdiffstats
path: root/cpu/mpc8xxx/ddr/options.c
Commit message (Expand)AuthorAgeFilesLines
* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-131-297/+0
* fsl-ddr: change the default burst mode for DDR3Dave Liu2010-04-071-4/+10
* fsl-ddr: add the override for write levelingDave Liu2010-01-051-0/+1
* fsl-ddr: Fix the chip-select interleaving issueDave Liu2009-11-121-4/+3
* fsl-ddr: add the DDR3 SPD infrastructureDave Liu2009-03-301-5/+23
* fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controllerKumar Gala2009-02-161-0/+4
* fsl-ddr: use the 1T timing as default configurationDave Liu2009-01-231-1/+1
* fsl ddr skip interleaving if not supported.Ed Swarthout2008-12-031-10/+10
* Check DDR interleaving modeHaiying Wang2008-10-181-5/+75
* Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-181-1/+3
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-271-0/+197