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* common: Move some board functions out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | A number of board function belong in init.h with the others. Move them. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* common: Move get_ticks() function out of common.hSimon Glass2019-12-021-0/+1
| | | | | | | This function belongs in time.h so move it over and add a comment. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com>
* arm64: versal: Move common board dtb searchIbai Erkiaga2019-10-081-0/+1
| | | | | | | | Move the exisiting function of getting board dtb from versal to a common Xilinx folder. Signed-off-by: Ibai Erkiaga <ibai.erkiaga-elorza@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Add new dfu usb distro boot commandT Karthik Reddy2019-10-081-0/+4
| | | | | | | This patch adds new dfu usb distro boot command to look for bootscript from dfu-util and runs it. Signed-off-by: T Karthik Reddy <t.karthik.reddy@xilinx.com>
* arm64: versal: Add new jtag distro boot commandSiva Durga Prasad Paladugu2019-10-081-1/+1
| | | | | | | | | | This patch adds new jtag distro boot command to look for bootscript file in DDR and execute it first incase of jtag bootmode. This patch also updates scriptaddr to 512MB as there is high of script corruption incase of bigger kernel image. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Enable memory mapping via DTMichal Simek2019-10-081-1/+8
| | | | | | | Code reads DT and setup MMU table based on memory node. This will ensure that only DT needs to be changed. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Set initrd_high to as high as possibleSiva Durga Prasad Paladugu2019-10-081-0/+6
| | | | | | | | | This patch is setting up the initrd_high to as high as possible by leaving max stack size for u-boot so that bigger rootfs can also be loaded by u-boot for booting kernel. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: fpga: Add PL bit stream load supportSiva Durga Prasad Paladugu2019-10-081-0/+10
| | | | | | | | | This patch adds PL bitstream load support for Versal platform. The PL bitstream is loaded by making an SMC to ATF which in turn communicates with platform firmware which configures and loads PL bitstream on to PL. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Define board_late_init for versalSiva Durga Prasad Paladugu2019-10-081-0/+111
| | | | | | | | | | | | | | Define board_late_init which performs bootmode detection and prepares corresponding distro boot commaand sequence. Also disable it for mini platforms because simply there is no need to have it enabled. But also disable it for virtual platform because Qemu is not modelling this register space that's why travis testing would fail. This configuration should be reverted when mainline Qemu is updated. Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Move IOU_SWITCH_DIVISOR0 to KconfigMichal Simek2019-02-141-1/+4
| | | | | | | Move hardcoded IOU_SWITCH_DIVISOR0 to Kconfig to be able to set it up for different platforms. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Remove one level of indentation in board_early_init_r()Michal Simek2019-02-141-36/+37
| | | | | | Simplify code indentation. Signed-off-by: Michal Simek <michal.simek@xilinx.com>
* arm64: versal: Add support for new Xilinx Versal ACAPsMichal Simek2018-10-163-0/+95
Xilinx is introducing Versal, an adaptive compute acceleration platform (ACAP), built on 7nm FinFET process technology. Versal ACAPs combine Scalar Processing Engines, Adaptable Hardware Engines, and Intelligent Engines with leading-edge memory and interfacing technologies to deliver powerful heterogeneous acceleration for any application. The Versal AI Core series has five devices, offering 128 to 400 AI Engines. The series includes dual-core Arm Cortex™-A72 application processors, dual-core Arm Cortex-R5 real-time processors, 256KB of on-chip memory with ECC, more than 1,900 DSP engines optimized for high-precision floating point with low latency. The patch is adding necessary infrastructure in place without enabling platform which is done in separate patch. Signed-off-by: Michal Simek <michal.simek@xilinx.com>