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| * | | | gpio: sandbox: Use a separate flag for the valueSimon Glass2021-03-031-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present with the sandbox GPIO driver it is not possible to change the value of GPIOD_IS_OUT_ACTIVE unless the GPIO is an output. This makes it hard to test changing the flags since we need to be aware of the internal workings of the driver. The feature is designed to aid testing. Split this feature out into a separate sandbox-specific flag, so that the flags can change unimpeded. This will make it easier to allow updating the flags in a future patch. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | gpio: sandbox: Rename GPIO dir_flags to flagsSimon Glass2021-03-031-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Adjust the terminology in this driver to reflect that fact that all flags are handled, not just direction flags. Create a new access function to get the full GPIO state, not just the direction flags. Drop the static invalid_dir_flags since we can rely on a segfault if something is wrong. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | sandbox: Write out bloblist when exitingSimon Glass2021-03-021-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Sandbox provides a way to write out its emulated memory on exit. This makes it possible to pass a bloblist from one phase (e.g. SPL) to the next. However the bloblist is not closed off, so the checksum is generally invalid. Fix this by finishing up the bloblist before writing the memory file. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | sandbox: Avoid using malloc() for system stateSimon Glass2021-03-024-29/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This state is not accessible to the running U-Boot but at present it is allocated in the emulated SDRAM. This doesn't seem very useful. Adjust it to allocate from the OS instead. The RAM buffer is currently not freed, but should be, so add that into state_uninit(). Update the comment for os_free() to indicate that NULL is a valid parameter value. Note that the strdup() in spl_board_load_image() is changed as well, since strdup() allocates memory in the RAM buffer. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | sandbox: Add os_realloc()Simon Glass2021-03-021-0/+48
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We provide os_malloc() and os_free() but not os_realloc(). Add this, following the usual semantics. Also update os_malloc() to behave correctly when passed a zero size. Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
| * | | | s5p4418_nanopi2: Drop dead codeSimon Glass2021-03-022-146/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This code is still using the old command typedef. It was not noticed since this file is not currently built. It is using a non-existent option in the Makefile. Drop this file since it is not needed for correct operation. Signed-off-by: Simon Glass <sjg@chromium.org>
| * | | | arm: remove set_dacr/get_dacr functionsPatrick Delaunay2021-03-021-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the unused function set_dacr/get_dacr Serie-cc: Ard Biesheuvel <ardb@kernel.org> Serie-cc: R Sricharan <r.sricharan@ti.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | arm: cp15: remove weak function arm_init_domainsPatrick Delaunay2021-03-023-10/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the unused weak function arm_init_domains used to change the DACR value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | arm: omap2: remove arm_init_domainsPatrick Delaunay2021-03-021-17/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the arm_init_domains and the DACR update, as it is now done in ARMv7 CP15 level. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | arm: cp15: update DACR value to activate access controlPatrick Delaunay2021-03-021-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the initial value of Domain Access Control Register (DACR) and set by default the access permission to client (DACR_Dn_CLIENT = 1U) for each of the 16 domains and no more to all-supervisor (DACR_Dn_MANAGER = 3U). This patch allows to activate the domain checking in MMU against the permission bits in the translation tables and avoids prefetching issue on ARMv7 [1]. Today it was already done for OMAP2 architecture ./arch/arm/mach-omap2/omap-cache.c::arm_init_domains introduced by commit de63ac278cba ("ARM: mmu: Set domain permissions to client access") which fixes lot of speculative prefetch aborts seen on OMAP5 secure devices. [1] https://developer.arm.com/documentation/ddi0406/b/System-Level-Architecture/Virtual-Memory-System-Architecture--VMSA-/Memory-access-control/The-Execute-Never--XN--attribute-and-instruction-prefetching Signed-off-by: Patrick Delaunay <patrick.delaunay@st.com> Reported-by: Ard Biesheuvel <ardb@kernel.org> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | arm: cosmetic: align TTB_SECT define valuePatrick Delaunay2021-03-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Align TTB_SECT define value with previous value. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | arm: remove TTB_SECT_XN_MASK in DCACHE_WRITETHROUGHPatrick Delaunay2021-03-021-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The normal memory (other that DCACHE_OFF) should be executable by default, only the device memory (DCACHE_OFF) used for peripheral access should have the bit execute never (TTB_SECT_XN_MASK). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | stm32mp: update the mmu configuration for SPL and prerelocPatrick Delaunay2021-03-021-10/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Overidde the weak function dram_bank_mmu_setup() to set the DDR (preloc case) or the SYSRAM (in SPL case) executable before to enable the MMU and configure DACR. This weak function is called in dcache_enable/mmu_setup. This patchs avoids a permission access issue when the DDR is marked executable (by calling mmu_set_region_dcache_behaviour with DCACHE_DEFAULT_OPTION) after MMU setup and domain access permission activation with DACR in dcache_enable. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | stm32mp: update MMU config before the relocationPatrick Delaunay2021-03-021-4/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mark the top of ram, used for relocated U-Boot as a normal memory (cacheable and executable) to avoid permission access issue when U-Boot jumps to this relocated code. When MMU is activated in pre-reloc stage; only the beginning of DDR is marked executable. This patch avoids access issue when DACR is correctly managed. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | | | reset: Remove addr parameter from reset_cpu()Harald Seiler2021-03-0264-71/+71
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically, the reset_cpu() function had an `addr` parameter which was meant to pass in an address of the reset vector location, where the CPU should reset to. This feature is no longer used anywhere in U-Boot as all reset_cpu() implementations now ignore the passed value. Generic code has been added which always calls reset_cpu() with `0` which means this feature can no longer be used easily anyway. Over time, many implementations seem to have "misunderstood" the existence of this parameter as a way to customize/parameterize the reset (e.g. COLD vs WARM resets). As this is not properly supported, the code will almost always not do what it is intended to (because all call-sites just call reset_cpu() with 0). To avoid confusion and to clean up the codebase from unused left-overs of the past, remove the `addr` parameter entirely. Code which intends to support different kinds of resets should be rewritten as a sysreset driver instead. This transformation was done with the following coccinelle patch: @@ expression argvalue; @@ - reset_cpu(argvalue) + reset_cpu() @@ identifier argname; type argtype; @@ - reset_cpu(argtype argname) + reset_cpu(void) { ... } Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
| * | | | Revert "lpc32xx: cpu: add support for soft reset"Harald Seiler2021-03-021-16/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This reverts commit 576007aec9a4a5f4f3dd1f690fb26a8c05ceb75f. The parameter passed to reset_cpu() no longer holds a meaning as all call-sites now pass the value 0. Thus, branching on it is essentially dead code and will just confuse future readers. Revert soft-reset support and just always perform a hard-reset for now. This is a preparation for removal of the reset_cpu() parameter across the entire tree in a later patch. Fixes: 576007aec9a4 ("lpc32xx: cpu: add support for soft reset") Cc: Sylvain Lemieux <slemieux@tycoint.com> Signed-off-by: Harald Seiler <hws@denx.de>
| * | | | nds32: Remove dead reset_cpu() implementationHarald Seiler2021-03-021-22/+0
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | nds32 is one of the only architectures which still have a reset_cpu() implementation that makes use of the `addr` parameter. The rest of U-Boot now ignores it and passes 0 everywhere. It turns out that even here, reset_cpu() is no longer referenced anywhere; reset is either not implemented (e.g. ae3xx) or realized using a WDT (e.g. ag101). Remove this left-over implementation in preparation for the removal of the `addr` parameter in the entire tree. Cc: Rick Chen <rick@andestech.com> Signed-off-by: Harald Seiler <hws@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Rick Chen <rick@andestech.com>
* | | | sunxi: dts: H616: Drop reserved-memory nodeAndre Przywara2021-03-311-12/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Trusted Firmware now adds the /reserved-memory subnode to the DT at runtime[1], putting in the right values. Drop our hard-coded version, as this might clash with the actual values (which have also changed), and rely on TF-A to add the node. [1] https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/7770 Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org> Reviewed-by: Jagan Teki <jagan@amarulasolutions.com>
* | | | sunxi: H616: Change TF-A load address to beginning of DRAMAndre Przywara2021-03-311-1/+1
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Loading Trusted-Firmware's BL31 at 16KB into DRAM was originally a hack to allow sharing more code with the other SoCs (which use this offset in SRAM). However there is no longer a reason for that, as the problematic macros have been properly separated there. The latest (and hopefully final) TF-A code drop now changes the load address to the beginning of DRAM, which is also more easily protected by the Trustzone memory controller (code to be done). Adjust the load address of BL31 now, to avoid any issues with incompatible versions later on (the TF-A patches are about to be merged). Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
* | | Merge https://gitlab.denx.de/u-boot/custodians/u-boot-fsl-qoriqTom Rini2021-03-241-0/+8
|\ \ \ | | | | | | | | | | | | | | | | - Bug fixes related to FSL-IFC, watchdog - layerscape-pcie, flexspi, T2080rdb.
| * | | powerpc: t2080rdb: Enable RTC supportChris Packham2021-03-231-0/+8
| | |/ | |/| | | | | | | | | | | | | | | | | | | The T2080RDB has a ds1339 on i2c0. Add this to the devicetree and enable the relevant support in the configs. Signed-off-by: Chris Packham <judge.packham@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* / | arm: socfpga: Only do 'is OS booted from FIT' checking when VAB is enabledSiew Chin Lim2021-03-231-1/+2
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Check CONFIG_SOCFPGA_SECURE_VAB_AUTH before perform 'is OS booted from FIT' checking in board_prep_linux function. And, fix typo of CONFIG_SOCFPGA_SECURE_VAB_AUTH_ALLOW_NON_FIT_IMAGE. CONFIG_FIT will be enabled in both ATF and VAB boot flow, thus, board_prep_linux function will always be called by both ATF and VAB boot flow. board_pre_linux function will do 'is OS booted from FIT' checking, and it will be called before board_fit_image_post_process function. VAB boot flow expects the OS is always booted from FIT and with VAB signed cerfiticate because the VAB authentication is implemented in board_fit_image_post_process function. So, VAB needs the 'is OS booted from FIT' checking in board_pre_linux function. However, for ATF boot flow, it is not a requirement that the OS must always booted from FIT. The OS can be booted from individual Image and kernel dtb file. Thus, we should not do 'if OS is booted from FIT' checking in board_prep_linux function. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | Merge tag 'u-boot-stm32-20210312' of ↵Tom Rini2021-03-1510-59/+101
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://source.denx.de/u-boot/custodians/u-boot-stm - Add WATCHDOG_RESET() in MTD framework and STM32 QSPI driver - stm32mp1_trusted_defconfig rely on SCMI support - Remove the nand MTD configuration for NOR boot in stm32mp1 board - STM32programmer update - Bsec: manage clock when present in device tree - stm32mp15: move bootdelay configuration in defconfig - Update for stm32 dsi and dw_mipi_dsi - STM32 MCU's cleanup - Fix compilation issue depending on SYS_DCACHE_OFF and SYS_ICACHE_OFF flags - Update stm32mp1 doc
| * | arm: stm32mp: Fix compilation issue when SYS_DCACHE_OFF and/or ↵Patrice Chotard2021-03-121-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | SYS_DCACHE_SYS are enabled Fix following compilation issue when SYS_DCACHE_OFF and/or SYS_DCACHE_SYS are enabled : arch/arm/mach-stm32mp/cpu.c: In function ‘early_enable_caches’: arch/arm/mach-stm32mp/cpu.c:223:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_size’ 223 | gd->arch.tlb_size = PGTABLE_SIZE; | ^ arch/arm/mach-stm32mp/cpu.c:224:10: error: ‘volatile struct arch_global_data’ has no member named ‘tlb_addr’ 224 | gd->arch.tlb_addr = (unsigned long)&early_tlb; | ^ Signed-off-by: Patrice Chotard <patrice.chotard@st.com> Signed-off-by: Patrice Chotard <patrice.chotard@foss.st.com> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
| * | stm32mp: bsec: manage clock when present in device treePatrick Delaunay2021-03-111-0/+10
| | | | | | | | | | | | | | | | | | | | | Enable the clocks during bsec probe when they are present in device tree. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| * | stm32mp: stm32prog: replace alias by serial device sequence numberPatrick Delaunay2021-03-112-30/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The command "stm32prog serial <dev>" can directly use the device sequence number of serial uclass as this sequence number is egual to alias when it exist; this assumption simplify the code and avoid access to gd->fdt_blob and the device tree parsing. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| * | stm32mp: stm32prog: reactivate console and display serial errorPatrick Delaunay2021-03-111-4/+10
| | | | | | | | | | | | | | | | | | | | | | | | When serial instance is not found in device tree, the console should be enabled and the error should be indicated. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| * | stm32mp: stm32prog: Add CONFIG_CMD_STM32PROG_SERIAL and _USBPatrick Delaunay2021-03-116-12/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Add CONFIG_CMD_STM32PROG_SERIAL and CONFIG_CMD_STM32PROG_USB to independently select the support of UART or USB communication for STM32CubeProgrammer. For serial boot over UART, user can deactivate CONFIG_CMD_STM32PROG_SERIAL to use U-Boot console of binary loaded by UART (for board bring-up for example). Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| * | stm32mp: stm32prog: Add Kconfig file for stm32prog commandPatrick Delaunay2021-03-112-17/+19
| | | | | | | | | | | | | | | | | | | | | Move CONFIG_CMD_STM32PROG in a specific Kconfig file for stm32prog command. Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
| * | ARM: dts: stm32mp1: explicit clock reference needed by RCC clock driverEtienne Carriere2021-03-111-0/+4
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define in the RCC clock provider node which root clocks the driver depends on. These are root oscillators, which may be present or not, upon FDT content. This update binding is introduced in Linux kernel device tree by patch "ARM: dts: stm32: move clocks/resets to SCMI resources for stm32mp15" This patch is a preliminary step for SCMI support of stm32mp15 boards with trusted boot chain, based on TF-A or OP-TEE. Signed-off-by: Etienne Carriere <etienne.carriere@st.com> Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
* | arm: mvebu: a38x: Remove dead code ARMADA_39XPali Rohár2021-03-124-106/+1
| | | | | | | | | | | | | | | | | | | | | | Config option ARMADA_39X is never set so remove all dead code hidden under ifdef CONFIG_ARMADA_39X blocks. Also remove useless checks for CONFIG_ARMADA_38X define as this macro is always defined for a38x code path. Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
* | x86: Select advanced Intel code only if allowedSimon Glass2021-03-092-0/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At present most of the Intel-specific code is built on all devices, even those which don't have software support for the features provided there. This means that any board can enable CONFIG_INTEL_ACPIGEN even if it does not have the required features. Add a new INTEL_SOC option to control this access. This must be selected by SoCs that can support the required features. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Move INTEL_ACPIGEN to arch/x86Simon Glass2021-03-091-0/+9
| | | | | | | | | | | | | | | | | | | | | | This option is better placed in the x86 code since it is not generic enough to be in the core code. Move it. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> [bmeng: fixed a typo in arch/x86/Kconfig] Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: Fix member check in intel_gnvsSimon Glass2021-03-091-0/+4
| | | | | | | | | | | | | | | | When CONFIG_CHROMEOS is not enabled this currently does not build. Fix it. Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | x86: sizeof-array-div error in lpc_common_early_initHeinrich Schuchardt2021-03-091-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Building qemu-x86_64_defconfig with GCC 11.0 fails with: arch/x86/cpu/intel_common/lpc.c: In function ‘lpc_common_early_init’: arch/x86/cpu/intel_common/lpc.c:56:40: error: expression does not compute the number of elements in this array; element type is ‘struct reg_info’, not ‘u32’ {aka ‘unsigned int’} [-Werror=sizeof-array-div] 56 | sizeof(values) / sizeof(u32)); | ^ arch/x86/cpu/intel_common/lpc.c:56:40: note: add parentheses around the second ‘sizeof’ to silence this warning arch/x86/cpu/intel_common/lpc.c:50:11: note: array ‘values’ declared here 50 | } values[4], *ptr; | ^~~~~~ Add parentheses to silence warning. Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
* | arm: socfpga: dts: soc64: Update filename in binman node of FIT image with ↵Siew Chin Lim2021-03-081-0/+22
| | | | | | | | | | | | | | | | VAB support FIT image of Vendor Authentication Coot (VAB) contains signed images. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: cmd: Support 'vab' commandSiew Chin Lim2021-03-082-0/+35
| | | | | | | | | | | | | | | | | | Support 'vab' command to perform vendor authentication. Command format: vab addr len Authorize 'len' bytes starting at 'addr' via vendor public key Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | arm: socfpga: soc64: Support Vendor Authorized Boot (VAB)Siew Chin Lim2021-03-086-4/+308
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Vendor Authorized Boot is a security feature for authenticating the images such as U-Boot, ARM trusted Firmware, Linux kernel, device tree blob and etc loaded from FIT. After those images are loaded from FIT, the VAB certificate and signature block appended at the end of each image are sent to Secure Device Manager (SDM) for authentication. U-Boot will validate the SHA384 of the image against the SHA384 hash stored in the VAB certificate before sending the image to SDM for authentication. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com> Reviewed-by: Ley Foon Tan <ley.foon.tan@intel.com>
* | arm: socfpga: Move Stratix10 and Agilex to use TARGET_SOCFPGA_SOC64Siew Chin Lim2021-03-084-7/+10
| | | | | | | | | | | | Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex. Signed-off-by: Siew Chin Lim <elly.siew.chin.lim@intel.com>
* | ppc: qemu: Move board directory from board/freescale to board/emulationBin Meng2021-03-051-1/+1
| | | | | | | | | | | | | | | | | | | | board/emulation is the place for other QEMU targets like x86, arm, riscv. Let's move the qemu-ppce500 board codes there. List me as a co-maintainer for this board. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | gpio: mpc8xxx: Support controller register physical address beyond 32-bitBin Meng2021-03-051-1/+1
| | | | | | | | | | | | | | | | | | dev_read_addr_size_index() returns fdt_addr_t which might be a 64-bit physical address. This might be true for some 85xx SoCs whose CCSBAR is mapped beyond 4 GiB. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | ppc: mpc85xx: Add 'gpibe' register to 'struct ccsr_gpio'Bin Meng2021-03-051-0/+1
| | | | | | | | | | | | | | | | Without this, the DM GPIO driver for MPC8xxx does not compile for MPC85xx SoCs. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | ppc: io.h: Use addrmap_ translation APIs only in post-relocation phaseBin Meng2021-03-051-6/+9
| | | | | | | | | | | | | | | | | | | | | | | | In phys_to_virt() and virt_to_phys(), if CONFIG_ADDR_MAP is defined, they use addrmap_ translation APIs to do the address translation. However these APIs only work in post-relocation phase. Update the code logic to fall back to use the default one when in pre-relocation phase. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | ppc: mpc85xx: Wrap LAW related codes with CONFIG_FSL_LAWBin Meng2021-03-052-0/+4
| | | | | | | | | | | | | | LAW related codes should be wrapped with CONFIG_FSL_LAW. Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | configs: fsl: move via specific defines to KconfigRajesh Bhagat2021-03-051-0/+6
| | | | | | | | | | | | | | | | | | | | Moves below via specific defines to Kconfig: CONFIG_FSL_VIA Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> [Rebased] Signed-off-by: Priyanka Jain <priyanka.jain@nxp.com>
* | configs: fsl: move bootrom specific defines to KconfigRajesh Bhagat2021-03-052-2/+10
| | | | | | | | | | | | | | | | | | | | Moves below bootrom specific defines to Kconfig: CONFIG_SYS_FSL_BOOTROM_BASE CONFIG_SYS_FSL_BOOTROM_SIZE Signed-off-by: Rajesh Bhagat <rajesh.bhagat@nxp.com> Reviewed-by: Priyanka Jain <priyanka.jain@nxp.com>
* | Merge tag 'u-boot-imx-20210303' of ↵Tom Rini2021-03-0334-11/+5644
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | https://gitlab.denx.de/u-boot/custodians/u-boot-imx i.MX for 2021.04 ---------------- - new boards: - i.MX8MN Beacon EmbeddedWorks (2GB) - Gateworks Venice imx8mm - convert to DM: - imx53-qsb, mx53loco, mx51evk, mx23-evk - Fixes : - Network : FEC ethernet quirks - DH dh-imx6 CI: https://source.denx.de/u-boot/custodians/u-boot-imx/-/pipelines/6597
| * | board: gateworks: imx8mm: Add Gateworks Venice board supportTim Harvey2021-03-037-0/+382
| | | | | | | | | | | | | | | | | | | | | Add initial support for Gateworks Venice product family based on the i.MX 8M Mini SoC Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | arm: dts: imx8mm: add Gateworks i.MX8 Mini Dev kitsTim Harvey2021-03-038-0/+1415
| | | | | | | | | | | | | | | | | | Add Gateworks i.MX 8M Mini Development kits from Linux-5.12-rc1 Signed-off-by: Tim Harvey <tharvey@gateworks.com>
| * | ARM: imx: Include u-boot.img in u-boot-with-spl.imx if OF_SEPARATE=yMarek Vasut2021-03-011-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The u-boot-with-spl.imx is a concatenation of SPL and u-boot.uim. The u-boot.uim is u-boot.bin wrapped in uImage. In case OF_SEPARATE is enabled, the u-boot.bin does not contain control DT for U-Boot, and so u-boot.uim does not contain the DT, and so u-boot-with-spl.imx does not contain the DT, and a system where u-boot-with-spl.imx is written to offset 1024B to the start of storage no longer boots, as it is missing DT. In case OF_SEPARATE is enabled, u-boot.img contains both u-boot.bin and the necessary DTs. Therefore, use u-boot.img instead of u-boot.uim to generate u-boot-with-spl.imx when OF_SEPARATE is enabled. Signed-off-by: Marek Vasut <marex@denx.de> Cc: Christoph Niedermaier <cniedermaier@dh-electronics.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: Peng Fan <peng.fan@nxp.com> Cc: Simon Glass <sjg@chromium.org> Cc: Stefano Babic <sbabic@denx.de> Cc: Ye Li <ye.li@nxp.com> Cc: uboot-imx <uboot-imx@nxp.com>
generated by cgit (git 2.34.1) at 2025-09-30 09:05:41 +0000